cant boot to dash jasper BB cpukey obtained via rgh2

xxdylanxx · Oct 27, 2013

Console Type: jasper
NAND size: 512
Dashboard version: 16537
CB version: e.g 5774
J-Runner log:
Description of problem:

Was the console working before you started: Y

Code:

===================================================Lunes, Oktubre 28, 2013 12:53:11 AM


J-Runner v0.3 Beta (2) Started




It's advised to run in administrator mode on Windows 8
WARNING! - Your selected working directory already contains files!
You can view these files by using 'Show Working Folder' Button




Checking Files
Finished Checking Files
Version: 10
Flash Config: 0x00AA3020
00AA3020
Jasper 512MB
CB Version: 6754
Version: 10
Flash Config: 0x00AA3020
00AA3020
Jasper 512MB
CB Version: 6754
Jasper 512MB Manually Selected
Reading Nand to D:\xbox\J-Runner_0.3_b1\output\nanddump1.bin
Reading Nand
Done!
in 13:21 min:sec


Reading Nand to D:\xbox\J-Runner_0.3_b1\output\nanddump2.bin
Initializing nanddump1.bin..
Jasper 512MB
Jtag Selected
Nand Initialization Finished
Reading Nand
Done!
in 13:20 min:sec


Comparing...Takes a while on big nands
Nands are the same
R-Jtag Selected
Patching Jasper version 2.3 SMC at offset 0x12BA
XeLL file created Successfully jasper_bb.bin
Version: 10
Flash Config: 0x00AA3020
Writing Nand
jasper_bb.bin
Done!
in 0:18 min:sec


Aud_Clamp Selected
Aud_Clamp de-Selected
Aud_Clamp Selected
Opus Manually Selected
Trinity Manually Selected
Jasper 256MB Manually Selected
Patching Jasper version 2.3 SMC at offset 0x12BA
XeLL file created Successfully jasper_hack_bigblock_aud_clamp.bin
Checking Console..
Version: 10
Flash Config: 0x00AA3020
00AA3020
Jasper 512MB
CB Version: 6723
Initializing nanddump1.bin..
Jasper BB
Nand Initialization Finished
Initializing nanddump1.bin..
Jasper BB
Nand Initialization Finished
R-Jtag de-Selected
Aud_Clamp de-Selected
Retail Selected
Jtag Selected
Aud_Clamp Selected
R-Jtag Selected
R-Jtag de-Selected
R-Jtag Selected
Initializing nandflash.bin..
Jasper 16MB
Nand Initialization Finished
Initializing nanddump1.bin..
Jasper BB
Nand Initialization Finished
Saving to D:\xbox\J-Runner_0.3_b1\output\nanddump1_edited.bin
Index was outside the bounds of the array.
Done
Initializing nanddump1_edited.bin..
Jasper BB
Nand Initialization Finished
Saving to D:\xbox\J-Runner_0.3_b1\output\nanddump1_edited_edited.bin
Index was outside the bounds of the array.
Done
Extracting..
Saving SMC_en.bin
Saving SMC_dec.bin
Saving KV_en.bin
Saving smc_config.bin
Finished
Initializing nanddump1_edited_edited.bin..
Jasper BB
Nand Initialization Finished
Initializing nanddump1.bin..
Jasper 16MB
Nand Initialization Finished
Initializing flashdmp_2.bin..
Jasper 512MB
Nand Initialization Finished
Initializing nanddump1.bin..
Jasper 16MB
Nand Initialization Finished
Initializing nandflash.bin..
Jasper 16MB
Nand Initialization Finished
Initializing nanddump1.bin..
Jasper 16MB
Nand Initialization Finished
Initializing nanddump1.bin..
Jasper BB
Nand Initialization Finished
Initializing nanddump1.bin..
Jasper BB
Nand Initialization Finished
Initializing nandflash.bin..
Jasper 16MB
Nand Initialization Finished
Initializing nandflash.bin..
Trinity
R-Jtag de-Selected
Aud_Clamp de-Selected
RGH2 Selected
Nand Initialization Finished
Initializing nandflash.bin..
Jasper 16MB
Jtag Selected
Nand Initialization Finished
Initializing nandflash.bin..
Jasper 16MB
Nand Initialization Finished
Initializing nandflash.bin..
Jasper 16MB
Nand Initialization Finished
Initializing nandflash.bin..
Jasper 16MB
Nand Initialization Finished
Initializing nanddump1.bin..
Jasper BB
Nand Initialization Finished
Initializing nanddump1.bin..
Jasper BB
Nand Initialization Finished
Comparing...Takes a while on big nands
Nands are the same
R-Jtag Selected
Aud_Clamp Selected
Patching Jasper version 2.3 SMC at offset 0x12BA
XeLL file created Successfully jasper_hack_bigblock_aud_clamp.bin
Version: 10
Flash Config: 0x00AA3020
Writing Nand
jasper_hack_bigblock_aud_clamp.bin
Done!
in 0:18 min:sec


R-Jtag de-Selected
RGH2 Selected
Jasper 512MB Manually Selected
ECC created
Jasper 512MB Manually Selected
Version: 10
Flash Config: 0x00AA3020
Writing Nand
image_00000000.ecc
Done!
in 0:18 min:sec


Initializing nanddump2.bin..
Too Many Bad Blocks
Too Many Bad Blocks
Jasper BB
Too Many Bad Blocks
Jtag Selected
Nand Initialization Finished
Jasper 512MB Manually Selected
Version: 10
Flash Config: 0x00AA3020
Writing Nand
nanddump2.bin
Done!
in 0:27 min:sec


Initializing nanddump2.bin..
Too Many Bad Blocks
Too Many Bad Blocks
Jasper BB
Too Many Bad Blocks
Nand Initialization Finished
Version: 10
Flash Config: 0x00AA3020
Writing Nand
image_00000000.ecc
Done!
in 0:18 min:sec


Power Up
Initializing nanddump1.bin..
Jasper BB
Nand Initialization Finished
Comparing...Takes a while on big nands
Nands are the same
RGH2 Selected
Jasper 512MB Manually Selected
ECC created
Jasper 512MB Manually Selected
Version: 10
Flash Config: 0x00000000
Can not Continue
Jasper 512MB Manually Selected
Version: 10
Flash Config: 0x00AA3020
Writing Nand
image_00000000.ecc
Done!
in 0:18 min:sec


Power Up
Shutdown
Programming Coolrunner
D:\xbox\J-Runner_0.3_b1\common\xsvf\TX_RGH2_B.xsvf
USB XSVF Player Initialized
Xilinx XC2C64A-VQ44 ......... [DETECTED]
Erase Succeeded
File: D:\xbox\J-Runner_0.3_b1\common\xsvf\TX_RGH2_B.xsvf
Sending Out Packets .........
Success
Getting info from ip 192.168.1.99...
LockDownValue is 4
Initializing nanddump1.bin..
CpuKey is Correct
Added Key to Database
Extracting..
Saving SMC_en.bin
Saving SMC_dec.bin
Saving KV_en.bin
Saving KV_dec.bin
Saving smc_config.bin
Finished
Jasper BB
Jtag Selected
Nand Initialization Finished
Moving All files from output folder to D:\xbox\J-Runner_0.3_b1\005948201808
Aud_Clamp Selected
R-Jtag Selected
Load Files Initiliazation Finished
Clean SMC detected
Patching Jasper version 2.3 SMC at offset 0x12BA
16537
Started Creation of the 16537 xebuild image
KV Info saved to file
---------------------------------------------------------------
     xeBuild v1.09.639
---------------------------------------------------------------
base path changed to D:\xbox\J-Runner_0.3_b1\xeBuild
---- { Image Build Mode } ----
building jtag image






****************  WARNING  *************************
  nanddump.bin has NAND memory unit data, make
  sure you back up any important data off the
  internal MU before flashing a new image!
****************************************************




******* WARNING: could not patch SMC reset limit!


---------------------------------------------------------------
D:\xbox\J-Runner_0.3_b1\005948201808\nandflash.bin image built, info:
---------------------------------------------------------------
Kernel    : 2.0.16537.0
Console   : Jasper (big block)
NAND size : 64MiB (system only)
Build     : JTAG
Xell      : power on console with console eject button
Serial    : 005948201808
ConsoleId : 013311779013
MoboSerial: 9177141110650188
Mfg Date  : 04/29/2020
CPU Key   : 7FF2318425B45CD2DD49F4CB90CC5842
1BL Key   : DD88AD0C9ED669E7B56794FB68563EFA
DVD Key   : 4E595421B3EC572F0320D69E0EDF0EF8
CF LDV    : 4
KV type   : type2 (hashed - unchecked, master key not available)
---------------------------------------------------------------
    xeBuild Finished. Have a nice day.
---------------------------------------------------------------
Saved to D:\xbox\J-Runner_0.3_b1\005948201808
Image is Ready
Version: 10
Flash Config: 0x00AA3020
Writing Nand
jasper_hack_bigblock_aud_clamp.bin
Done!
in 0:01 min:sec


Version: 10
Flash Config: 0x00AA3020
Writing Nand
edited.bin
Done!
in 0:18 min:sec
Initializing edited.bin..


Jasper BB
Nand Initialization Finished
Patching Jasper version 2.3 SMC at offset 0x12BA
XeLL file created Successfully jasper_hack_bigblock_aud_clamp.bin
Version: 10
Flash Config: 0x00AA3020
Writing Nand
jasper_hack_bigblock_aud_clamp.bin
Done!
in 0:18 min:sec


Initializing nandflash.bin..
Jasper 16MB
Nand Initialization Finished
Initializing edited.bin..
Jasper BB
Nand Initialization Finished
Jasper 512MB Manually Selected
Version: 10
Flash Config: 0x00AA3020
Writing Nand
edited.bin
Done!
in 14:36 min:sec

Post rater log

Code:

Phat SelectedVersion: 10
Power Up
Waiting for POST to change
Post 16 - FETCH_HEADER 
Post 06 
Post 16 - FETCH_HEADER 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 24 - VERIFY_OFFSET_3BL_CC 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 0C 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 43 - VERIFY_HEADER 
Post 44 - FETCH_CONTENTS 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 18 - FETCH_CONTENTS 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 23 - INIT_SYSRAM 
Post 3B - PCI_INIT 
Post 40 - Entrypoint of CD reached 
Most Fails(cumulative): 0xA0
Shutdown
Power Up
Waiting for POST to change
Post 16 - FETCH_HEADER 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 24 - VERIFY_OFFSET_3BL_CC 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 32 - VERIFY_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 49 - SHA_VERIFY 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 23 - INIT_SYSRAM 
Post 31 - FETCH_HEADER_4BL_CD 
Post 3B - PCI_INIT 
Post 40 - Entrypoint of CD reached 
Most Fails(cumulative): 0xA0
Shutdown

heres the problem this unit was the one in this thread http://team-xecuter.com/forums/showthread.php?t=140420
i decided to update it to latest dash so i can rjtag it
so after update and rjtag install i cant get it to xell tried everything al dip settings, aud_clamp and default, 330 470,
stuck to this Post 11 - FSB_CONFIG_PHY_CONTROL if flash with aud_clamp_xell and solder it to normal(hoping to get e79)
i was following this thread http://team-xecuter.com/forums/showthread.php?t=138969 because we have the same issue Post 6F - INIT_POWER_MODE if soldered to the right connection post rater is almost perpect 90% @ 1 cycle but cant pass POST-11_FSB_CONFIG_PHY_CONTROL but the rater shuts the unit and cycles another boot, booted 30 times @ almost 1 cycle
i use 3 jtag qsb, now i installed dioide with same result everytime,

then i decided to take out rjtag and install cr3 for rgh2 to get the cpu key(and yes i did)
then back to jrunner and flashed the created Rjtag image, but still no luck, above is the post rater screenshots
rjtag image, tried to edit smc_config using 360 flash tool
i use other rjtag image as base for power mode and power vcs control flash the edited_rjtag image and still no luck
i think it the board manufactured april 2010 have issues(360 flash tool says april 2020

)
will post pics later i have to sleep its almost 6am here... i hope i get a good result later,.. BTW i flashed stock nand and i boots fine even the rater(de-soldered D and booted stocknand and ratered it with good result.. i havee to sleep now.. hopefully i can get this fixed thanks for reading

Martin C · Oct 27, 2013

You've posted no pics of your soldering.

xxdylanxx · Oct 28, 2013

my stock nand post rater..

my install pics

Code:

Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 16 - FETCH_HEADER 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Power Up
Waiting for POST to change
Post 06 
Post 04 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post E0 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 41 - VERIFY_OFFSET 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 49 - SHA_VERIFY 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Power Up
Waiting for POST to change
Post 06 
Post 04 
Post 19 - HMACSHA_COMPUTE 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Power Up
Waiting for POST to change
Post 06 
Post 04 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Power Up
Waiting for POST to change
Post 06 
Post 04 
Post F7 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 41 - VERIFY_OFFSET 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 49 - SHA_VERIFY 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Most Fails(cumulative): 0xA0
Shutdown
Power Up
Waiting for POST to change
Post 06 
Post 04 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Most Fails(cumulative): 0xA0
Shutdown
Power Up
Waiting for POST to change
Post 06 
Post 04 
Post 40 - Entrypoint of CD reached 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Most Fails(cumulative): 0xA0
Shutdown
Power Up
Waiting for POST to change
Post 06 
Post 04 
Post 0E 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Most Fails(cumulative): 0xA0
Shutdown
Power Up
Waiting for POST to change
Post 06 
Post 04 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 44 - FETCH_CONTENTS 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Most Fails(cumulative): 0xA0
Shutdown
Power Up
Waiting for POST to change
Post 16 - FETCH_HEADER 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Most Fails(cumulative): 0xA0
Shutdown
Reached No. of Boots Required

my post_output with xell flashed
seems to me its glitching good, but cant pass Post11

Martin C · Oct 28, 2013

POST 11 is xell. So it's actually booting. You should see the RoL cycle, something on screen or some activity via LAN.

It's shutting down the system as you're running RATER (that's what it does on a successful boot - I know, common sense). Just choose POST monitor instead.

xxdylanxx · Oct 28, 2013

Martin C said:
POST 11 is xell. So it's actually booting. You should see the RoL cycle, something on screen or some activity via LAN.

It's shutting down the system as you're running RATER (that's what it does on a successful boot - I know, common sense). Just choose POST monitor instead.

no ROL activity,. no boot sequence, no video on hdmi or av cable

Martin C · Oct 28, 2013

Nothing at all? Not even a red light and E79?

Write the stock NAND back and make sure it boots.

xxdylanxx · Oct 28, 2013

here's the post monitor.. no xell at all tried av cable and hdmi

Code:

===================================================Lunes, Oktubre 28, 2013 9:03:08 PM


J-Runner v0.3 Beta (2) Started




It's advised to run in administrator mode on Windows 8
WARNING! - Your selected working directory already contains files!
You can view these files by using 'Show Working Folder' Button




Checking Files
Finished Checking Files
Initializing jasper_hack_bigblock_aud_clamp.bin..
Too Many Bad Blocks
Header is wrong..
Too Many Bad Blocks
Jasper BB
Too Many Bad Blocks
Jtag Selected
Nand Initialization Finished
Jasper 256MB Manually Selected
Version: 10
Flash Config: 0x00AA3020
Writing Nand
jasper_hack_bigblock_aud_clamp.bin
Done!
in 0:18 min:sec


Version: 10
Press Escape to exit
Waiting for POST to change
Post 16 - FETCH_HEADER
Post 14 - FSB_CONFIG_TX_CREDITS
Post 04
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 14 - FSB_CONFIG_TX_CREDITS
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 04
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 04
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 14 - FSB_CONFIG_TX_CREDITS
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 14 - FSB_CONFIG_TX_CREDITS
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 04
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 14 - FSB_CONFIG_TX_CREDITS
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 14 - FSB_CONFIG_TX_CREDITS
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 04
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 14 - FSB_CONFIG_TX_CREDITS
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 14 - FSB_CONFIG_TX_CREDITS
Post E0
Post 10 - Payload/1BL started
Post 12 - FSB_CONFIG_RX_STATE
Post 15 - FETCH_OFFSET
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 49 - SHA_VERIFY
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL

xxdylanxx · Oct 28, 2013

Martin C said:
Nothing at all? Not even a red light and E79?

Write the stock NAND back and make sure it boots.

yes nothing,.. just did that a minutes ago. i also tried using donor nandflash to see if can boot
and still no, i also tried wiring normal , flashed with aud_clamp(hoping to see e79, better news for me) but still nothing at all

Martin C · Oct 28, 2013

So you have a hardware fault.

xxdylanxx · Oct 28, 2013

here's the post monitor booting to stock

Code:

===================================================Lunes, Oktubre 28, 2013 9:16:09 PM


J-Runner v0.3 Beta (2) Started




It's advised to run in administrator mode on Windows 8
WARNING! - Your selected working directory already contains files!
You can view these files by using 'Show Working Folder' Button




Checking Files
Finished Checking Files
Version: 10
Press Escape to exit
Waiting for POST to change
Post 16 - FETCH_HEADER
Post 14 - FSB_CONFIG_TX_CREDITS
Post 04
Post 14 - FSB_CONFIG_TX_CREDITS
Post 04
Post 14 - FSB_CONFIG_TX_CREDITS
Post 04
Post 14 - FSB_CONFIG_TX_CREDITS
Post 04
Post 14 - FSB_CONFIG_TX_CREDITS
Post 04
Post 14 - FSB_CONFIG_TX_CREDITS
Post 04
Post 14 - FSB_CONFIG_TX_CREDITS
Post 04
Post 14 - FSB_CONFIG_TX_CREDITS
Post 04
Post 14 - FSB_CONFIG_TX_CREDITS
Post 04
Post 14 - FSB_CONFIG_TX_CREDITS
Post 04
Post 14 - FSB_CONFIG_TX_CREDITS
Post 04
Post 14 - FSB_CONFIG_TX_CREDITS
Post 04
Post 14 - FSB_CONFIG_TX_CREDITS
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS
Post 5E - INIT_SOC_INT_COMPLETE
Post 5F
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 64 - INIT_MEMORY_MANAGER
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 6C - INIT_SECURITY
Post 6D - INIT_KEY_EX_VAULT
Post 6E - INIT_SETTINGS
Post 6F - INIT_POWER_MODE
Post 70 - INIT_VIDEO_DRIVER
Post 71 - INIT_AUDIO_DRIVER
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init
Post 73 - INIT_SATA_DRIVER
Post 75 - INIT_DUMP_SYSTEM
Post 76 - INIT_SYSTEM_ROOT
Post 77 - INIT_OTHER_DRIVERS
Post 78 - INIT_STFS_DRIVER
Post 79 - LOAD_XAM

xxdylanxx · Oct 28, 2013

Martin C said:
So you have a hardware fault.

its originally 8498, in my other post should be rgh1, i also mentioned that all april manufactured xbox that pass to my hand never actually boot to rgh1, i have to update it to rgh2...

i think not faulty hardware because i got cpukey in rgh2,. booted rgh2 nandflash,. within 6 cycle..

i also changed rjtag chip, post qsb, jtag qsb.

Martin C · Oct 28, 2013

Code:

Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL

That's xell booting right there. Get COM monitor hooked up and see what happens at this stage.

xxdylanxx · Oct 28, 2013

Martin C said:
Code:

Post 67 - INIT_PHASE1_THREAD Post 68 - Started phase 1 Initialization + INIT_PROCESSORS Post 69 - INIT_KEY_VAULT Post 6A - INIT_HAL_PHASE_1 Post 6B - INIT_SFC_DRIVER Post 10 - Payload/1BL started Post 11 - FSB_CONFIG_PHY_CONTROL

That's xell booting right there. Get COM monitor hooked up and see what happens at this stage.

tried that and also nothing..

xxdylanxx · Oct 28, 2013

after 30 minutes at this

Post 6A - INIT_HAL_PHASE_1Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL

still no activity.. should i give up and go for rgh2??

Martin C · Oct 28, 2013

What DIP/setting do you have the R-JTAG on?

xxdylanxx · Oct 28, 2013

Martin C said:
What DIP/setting do you have the R-JTAG on?

378 on,on,on best on rater 1-3 cycles
the default jasper 578 5 cycles or more to glitch., others not pretty good cycles

Martin C · Oct 28, 2013

There's not really a 'default' DIP, so don't get spooked on the DIP you're using. Each console type has 6 options for timing, so one of them should work.

What value resistor is that between J2D2.4 and J2D2.7?

xxdylanxx · Oct 29, 2013

Martin C said:
There's not really a 'default' DIP, so don't get spooked on the DIP you're using. Each console type has 6 options for timing, so one of them should work.

What value resistor is that between J2D2.4 and J2D2.7?

tried all DIP setting and votage settings without 1 boot.. stops at post11

resisitor is 100ohm as i have read here

http://www.free60.org/File:Reversejatg.jpg

i also tried bridged them with wire.. could be kv or smc??

Martin C · Oct 29, 2013

Try 470ohm instead.

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cant boot to dash jasper BB cpukey obtained via rgh2

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