I have other chips and I will try that to see if it boots stock and report results.
I had wrote back the stock nand, the console boots just fine, so I wrote the xell, wrote to the nand, unplugged then ran rater
Jrunner log
Code:
===================================================Thursday, December 18, 2014 5:42:02 PM
J-Runner v0.3 Beta (7) Started
WARNING! - Your selected working directory already contains files!
You can view these files by using 'Show Working Folder' Button
Checking Files
Finished Checking Files
Initializing nanddump1.bin..
Jasper BB
Jtag Selected
Aud_Clamp Selected
Nand Initialization Finished
R-Jtag Selected
Patching Jasper version 2.3 SMC at offset 0x12BA
XeLL file created Successfully jasper_hack_bigblock_aud_clamp.bin
Version: 10
Flash Config: 0x008A3020
Writing Nand
jasper_hack_bigblock_aud_clamp.bin
Done!
in 0:18 min:sec
Initializing nanddump1.bin..
Jasper BB
Nand Initialization Finished
Jasper 256MB Manually Selected
Version: 10
Flash Config: 0x008A3020
Writing Nand
nanddump1.bin
Done!
in 14:27 min:sec
Checking Console..
Version: 10
Flash Config: 0x00000000
Can not Continue
Can not continue
Checking Console..
Version: 10
Flash Config: 0x008A3020
008A3020
Jasper 256MB
CB Version: 6754
Initializing nanddump1.bin..
Jasper BB
Nand Initialization Finished
Patching Jasper version 2.3 SMC at offset 0x12BA
XeLL file created Successfully jasper_hack_bigblock_aud_clamp.bin
Version: 10
Flash Config: 0x008A3020
Writing Nand
jasper_hack_bigblock_aud_clamp.bin
Done!
in 0:18 min:sec
I hooked up rater and here is the log
Code:
[CODE]CR4 SelectedVersion: 10
Power Up
Waiting for POST to change
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Post 01 - .
Post 03 - ...
Post 04 - BOOT SEQUENCE STARTING
Post 05 - ...
Post 06 - ....
Post 07 - .....
Post 08 - ......
Post 09 - .......
Post 0A - ........
Post 0B - .........
Post 0C - ..........
Post 0D - GLITCH CHECK COMMENCE
Post 0E - CB_B ENTRY REACHED
Post 0F - GLITCH SUCCESSFUL
Post 10 - ......
Shutdown

I resoldered a couple points that were dull in color, re did the yellow wire, did not touch the blue or white. created xell, wrote xell, unplugged, ran rater, actaully stopped it at the glitch cycle cause it did not glitch at all. I'm not sure what to do next