R-JTAG Falcon boots xell but dash

dj0hackers · Dec 9, 2013

hi, i'm working on my falcon with 16537 dash to install r-jtag from but it wont's work!
I follow tx guide but nothing.
After installing both qsb to read nand i'we read it twice, i create xell reloaded (create sell reloaded key on jr), i have installed both r-jtag qsb whit aud_clamp and i've set first switch to on, jumper in 470 position, and the 3 way selector in to the central position, then i've wrote xell-reloaded( write xell-reloaded button on jr), i've powered on my console and i've got my cpu key from lan.
Well now i've clicked create xeBuild image button on jr and then write nand.
Now i'm trying to power up my console but r-jtag chip glichts and the central ring green led remains up but i can see nothing on screen.
i try to start console from eject button and in works well.
what can it be??
thanks for answers.

Martin C · Dec 9, 2013

[h=3]*** R-JTAG SUPPORT TEMPLATE - READ AND FOLLOW THIS BEFORE ASKING FOR ANY SUPPORT ***[/h]

dj0hackers · Dec 10, 2013

i'm sorry

Console Type: Falcon
NAND size: 16
Dashboard version: 2.0.16537
CB version: 5770
Screenshot of NAND details from J-Runner:

Code:

J-Runner v0.3 Beta (4) Started




Checking Files
Initializing nanddump1.bin..
Falcon/Opus
Jtag Selected
Nand Initialization Finished
Aud_Clamp Selected
R-Jtag Selected
Finished Checking Files
Load Files Initiliazation Finished
Clean SMC detected
Patching Jasper version 2.3 SMC at offset 0x12BA
16537
Started Creation of the 16537 xebuild image
KV Info saved to file
---------------------------------------------------------------
xeBuild v1.09.639
---------------------------------------------------------------
base path changed to \\psf\Home\Desktop\prova 2\J-Runner v03 (1) Core Pack\J-Runner\xeBuild
---- { Image Build Mode } ----
building jtag image




******* WARNING: could not patch SMC reset limit!


---------------------------------------------------------------
\\psf\Home\Desktop\prova 2\J-Runner v03 (1) Core Pack\J-Runner\010427784205\updflash.bin image built, info:
---------------------------------------------------------------
Kernel : 2.0.16537.0
Console : Falcon
NAND size : 16MiB
Build : JTAG
Xell : power on console with console eject button
Serial : 010427784205
ConsoleId : 027401361655
MoboSerial: 757853F202748425
Mfg Date : 10/14/2008
CPU Key : 07CF8------------------------------EBCDE56
1BL Key : DD88A------------------------------8563EFA
DVD Key : F8081------------------------------41285AE
CF LDV : 8
KV type : type2 (hashed - unchecked, master key not available)
---------------------------------------------------------------
xeBuild Finished. Have a nice day.
---------------------------------------------------------------
Saved to \\psf\Home\Desktop\prova 2\J-Runner v03 (1) Core Pack\J-Runner\010427784205
Image is Ready
Initializing updflash.bin..
Falcon/Opus
Nand Initialization Finished

Was the console working before you started: Y

jrunner rater log

Code:

Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 23 - INIT_SYSRAM
Post 31 - FETCH_HEADER_4BL_CD
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4D - DECODE_FUSES
Post 4E - FETCH_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS
Post 5F
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Shutdown
Power Up
Waiting for POST to change
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7C
Post 7F
Post 7F
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 42 - FETCH_HEADER
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 49 - SHA_VERIFY
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 18 - FETCH_CONTENTS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 23 - INIT_SYSRAM
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 47 - RC4_DECRYPT
Post 4B - LZX_EXPAND
Post 4D - DECODE_FUSES
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS
Post 5F
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Shutdown
Power Up
Waiting for POST to change
Post 07
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 61 - INIT_HAL_PHASE_0
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 23 - INIT_SYSRAM
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 4B - LZX_EXPAND
Post 4D - DECODE_FUSES
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS
Post 5F
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Shutdown
Power Up
Waiting for POST to change
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 03
Post 03
Post 03
Post 01
Post 03
Post 03
Post 01
Post 03
Post 01
Post 03
Post 03
Post 03
Post 03
Post 01
Post 03
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 41 - VERIFY_OFFSET
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 03
Post 03
Post 03
Post 03
Post 01
Post 03
Post 03
Post 03
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 03
Post 01
Post 01
Post 03
Post 01
Post 03
Post 01
Post 03
Post 01
Post 03
Post 01
Post 23 - INIT_SYSRAM
Post 03
Post 03
Post 01
Post 03
Post 03
Post 01
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 01
Post 01
Post 03
Post 03
Post 03
Post 01
Post 03
Post 03
Post 01
Post 03
Post 03
Post 01
Post 03
Post 03
Post 03
Post 03
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 03
Post 03
Post 03
Post 03
Post 01
Post 03
Post 03
Post 01
Post 01
Post 03
Post 01
Post 03
Post 01
Post 03
Post 03
Post 03
Post 01
Post 03
Post 01
Post 03
Post 03
Post 03
Post 03
Post 03
Most Fails(cumulative): 0x22
Shutdown
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 7F
Post 7F
Post 4F - VERIFY_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 01
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 23 - INIT_SYSRAM
Post 31 - FETCH_HEADER_4BL_CD
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4D - DECODE_FUSES
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS
Post 5F
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Shutdown
Power Up
Waiting for POST to change
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 03
Post 03
Post 01
Post 03
Post 01
Post 03
Post 01
Post 03
Post 03
Post 03
Post 01
Post 03
Post 03
Post 03
Post 03
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 42 - FETCH_HEADER
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 61 - INIT_HAL_PHASE_0
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 16 - FETCH_HEADER
Post 18 - FETCH_CONTENTS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 3B - PCI_INIT
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4D - DECODE_FUSES
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS
Post 5F
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Shutdown
Power Up
Waiting for POST to change
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 40 - Entrypoint of CD reached
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 01
Post 03
Post 01
Post 01
Post 03
Post 01
Post 01
Post 03
Post 01
Post 33 - FETCH_CONTENTS_4BL_CD
Post 03
Post 03
Post 01
Post 03
Post 01
Post 03
Post 01
Post 03
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 03
Post 01
Post 03
Post 01
Post 01
Post 03
Post 01
Post 03
Post 03
Post 01
Post 03
Post 03
Post 03
Post 03
Post 01
Post 03
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 03
Post 01
Post 03
Post 03
Post 03
Post 03
Post 01
Post 03
Post 01
Post 03
Post 01
Post 03
Post 03
Post 01
Post 01
Post 03
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 42 - FETCH_HEADER
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 15 - FETCH_OFFSET
Post 18 - FETCH_CONTENTS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 23 - INIT_SYSRAM
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 3B - PCI_INIT
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4D - DECODE_FUSES
Post 4E - FETCH_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS
Post 5F
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Most Fails(cumulative): 0x22
Shutdown
Power Up
Waiting for POST to change
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 3F
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 03
Post 01
Post 03
Post 03
Post 01
Post 03
Post 03
Post 01
Post 03
Post 03
Post 01
Post 03
Post 03
Post 01
Post 03
Post 03
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 01
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 03
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 42 - FETCH_HEADER
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 23 - INIT_SYSRAM
Post 31 - FETCH_HEADER_4BL_CD
Post 3B - PCI_INIT
Post 44 - FETCH_CONTENTS
Post 47 - RC4_DECRYPT
Post 4B - LZX_EXPAND
Post 4D - DECODE_FUSES
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS
Post 5F
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Most Fails(cumulative): 0x22
Shutdown
Power Up
Waiting for POST to change
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 03
Post 03
Post 01
Post 03
Post 03
Post 03
Post 01
Post 03
Post 03
Post 03
Post 01
Post 03
Post 01
Post 03
Post 03
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 43 - VERIFY_HEADER
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 16 - FETCH_HEADER
Post 18 - FETCH_CONTENTS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 23 - INIT_SYSRAM
Post 31 - FETCH_HEADER_4BL_CD
Post 3B - PCI_INIT
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4D - DECODE_FUSES
Post 4E - FETCH_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS
Post 5F
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 64 - INIT_MEMORY_MANAGER
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Most Fails(cumulative): 0x22
Shutdown
Power Up
Waiting for POST to change
Post 7F
Post 7F
Post 7F
Post 7F
Post 47 - RC4_DECRYPT
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 61 - INIT_HAL_PHASE_0
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4D - DECODE_FUSES
Post 4E - FETCH_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS
Post 5F
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Most Fails(cumulative): 0x22
Shutdown

i'm going to post the other pics

dj0hackers · Dec 10, 2013

i'm sorry but i can't upload other pictures because forum stops me. however my cpu_rst is the first one in the tx guide (C7R112)

chase · Dec 10, 2013

next time please use the CODE or QUOTE tags for lengthy logs

have you gone through all the dips, voltage, resistance and cpu_rst options ?

stopping at post 6x could be wiring issue i think (correct me if I'm wrong

)

please post pics of jtag qsb

does stock nand boot ? wonder if its SMC config

dj0hackers · Dec 10, 2013

chase said:
next time please use the CODE tags for lengthy logs

have you gone through all the dips, voltage, resistance and cpu_rst options ?

stopping at post 6x is wiring issue i think (correct me if I'm wrong )

please post pics of jtag qsb

i used code tag but it's not working however i've tried all possible dips combination, all voltages combinations and alternative cup_rst and also without aud_clamp but with the same results.

here the other pics
https://www.dropbox.com/s/qtg7f3zblkw2hsv/foto 1.JPG
https://www.dropbox.com/s/g3nfykn7v4v7j12/foto 2.jpg
https://www.dropbox.com/s/njkl3xlld15amcf/foto 5.jpg

chase · Dec 10, 2013

soldering look ok to me

can you switch off jtag qsb, remove 5v from r-jtag and try stock nand

Martin C · Dec 10, 2013

dj0hackers said:
i'm sorry but i can't upload other pictures because forum stops me

This is why we have stickies.

I made one entitled 'why can't I upload pictures?'.

Yes, it looks like it might be an SMC Config issue.

BTW, I don't like having to manually edit someones post because they're too stupid to use tags. We have buttons which put things in tags for you. If you can't click on a button or understand that you can't have spaces in tags, please refrain from posting.

dj0hackers · Dec 10, 2013

i only followed guide that martin c gave to me. Next time i'll use buttons.
However i've tried whit stock fw and it works and i've used all the possible smc configurations combination but no changes

that's the guide i've followed for smc

Just in case you need them for another Xbox 360:
The possible alternative values for Power Mode can be 8280 or 8380 or 8480
The possible alternative values for Power VCS Control can be 8555 or 8565
The possible alternative values for ANA Fuse Value can be 01 or 03

Martin C · Dec 10, 2013

Put everything back as-is and change Power Mode to 8080.

dj0hackers · Dec 10, 2013

Martin C said:
Put everything back as-is and change Power Mode to 8080.

now i am at university i'll try after 7.00 pm
thanks

dj0hackers · Dec 10, 2013

power mode modified to 8080 but there are no changes!
Console boots xell (with eject button) but dash.

rater results (it seems like before)

Code:

Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 04 
Post 7F 
Post 7F 
Post 7F 
Post 7F 
Post 6C - INIT_SECURITY 
Post 7F 
Post 7F 
Post 7F 
Post 7F 
Post 7F 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG
Post 2F - RELOCATE 
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE 
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER 
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY 
Post 1E - BRANCH
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG 
Post 2F - RELOCATE
Post 23 - INIT_SYSRAM 
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT
Post 4B - LZX_EXPAND 
Post 4D - DECODE_FUSES
Post 4E - FETCH_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH 
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS 
Post 5F
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Shutdown
Power Up
Waiting for POST to change
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 7F
Post 32 - VERIFY_HEADER_4BL_CD
Post 7F
Post 7F
Post 7F
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY 
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG
Post 03
Post 01 
Post 01 
Post 03
Post 01 
Post 03 
Post 01
Post 03
Post 01 
Post 01 
Post 03
Post 03
Post 01 
Post 03
Post 01
Post 03 
Post 01
Post 03
Post 01
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP
Post 87 - Panic - ALIGNMENT 
Post 03
Post 01
Post 01
Post 01
Post 03
Post 01 
Post 01 
Post 03 
Post 01
Post 01
Post 03 
Post 01
Post 03 
Post 01 
Post 01 
Post 03 
Post 01
Post 01
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG
Post 01
Post 03 
Post 03 
Post 01
Post 01
Post 01
Post 01
Post 03 
Post 01 
Post 03
Post 01
Post 03
Post 01 
Post 01 
Post 03 
Post 01
Post 01
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER 
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG 
Post 03
Post 01 
Post 03
Post 01
Post 01
Post 01
Post 01
Post 03 
Post 01
Post 01
Post 03
Post 01
Post 01
Post 03
Post 01 
Post 03 
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG 
Post 13 - FSB_CONFIG_TX_STATE
Post 03
Post 01
Post 03 
Post 01
Post 03
Post 01 
Post 03
Post 01 
Post 03 
Post 01 
Post 03
Post 01 
Post 01 
Post 01 
Post 03 
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG 
Post 03 
Post 01 
Post 03
Post 01 
Post 01 
Post 01 
Post 03 
Post 03 
Post 01
Post 01
Post 01
Post 01
Post 03
Post 01 
Post 03 
Post 03 
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG
Post 03 
Post 03 
Post 03 
Post 01
Post 01
Post FD 
Post 01 
Post 01 
Post 03
Post 01 
Post 03
Post 01 
Post 01 
Post 01 
Post 01 
Post 01 
Post 01 
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE 
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG 
Post 03
Post 01 
Post 03 
Post 01
Post 03
Post 03
Post 01
Post 03 
Post 01 
Post 01 
Post 03
Post 01
Post 03
Post 01 
Post 03
Post 01 
Post 01 
Post 01 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG
Post 01 
Post 03
Post 01
Post 03
Post 01
Post 01
Post 01
Post 01
Post 01
Post 03 
Post 01 
Post 01 
Post 01 
Post 01 
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY 
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP 
Post 87 - Panic - ALIGNMENT
Post 01
Post 03 
Post 01
Post 01
Post 01
Post 03 
Post 01 
Post 01 
Post 01 
Post 03
Post 03
Post 01 
Post 01 
Post 03
Post 01
Post 03
Post 01
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG
Post 03
Post 01
Post 03 
Post 01
Post 03 
Post 03 
Post 01
Post 01
Post 01
Post 03 
Post 03 
Post 01
Post 01
Post 03 
Post 03 
Post 01 
Post 03 
Post 03 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG
Post 03
Post 01 
Post 01 
Post 01 
Post 03 
Post 03 
Post 01 
Post 01 
Post 03
Post 01 
Post 03 
Post 01
Post 03
Post 01 
Post 01 
Post 01 
Post 03 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY 
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG
Post 03 
Post 01
Post 01
Post 01
Post 05
Post 01 
Post 03 
Post 01
Post BF 
Post 01 
Post 03 
Post 01 
Post 03 
Post 01
Post 03
Post 01 
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG 
Post 01
Post 01
Post 03 
Post 01
Post 03
Post 41 - VERIFY_OFFSET 
Post 01
Post 03 
Post 01
Post 01
Post 03
Post 01 
Post 01 
Post 03 
Post 01
Post 01
Post 03
Post 03
Post 01 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE 
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER 
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG 
Post 01
Post 01
Post 01
Post 03
Post 01 
Post 01 
Post 03
Post 01 
Post 03 
Post 01 
Post 01 
Post 03
Post 01
Post 01
Post 01
Post 01
Post 01
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG
Post 01
Post 01
Post 01
Post 03 
Post 03 
Post 01
Post 01
Post 01
Post 03 
Post 03 
Post 01
Post 01
Post 01
Post 01
Post 03
Post 03
Post 03
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG 
Post 2F - RELOCATE
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS 
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY
Post 1E - BRANCH 
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG
Post 2F - RELOCATE 
Post 23 - INIT_SYSRAM
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD
Post 3B - PCI_INIT 
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE 
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND 
Post 4D - DECODE_FUSES
Post 4E - FETCH_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH 
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS 
Post 5F
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Done!


Most Fails(cumulative): 0x21
Shutdown

i've stopped it after only 2 "boots"

dj0hackers · Dec 12, 2013

Somone can help me??

Martin C · Dec 12, 2013

There are other SMC values to try.

Check from here onwards.

gavin_darkglide · Dec 12, 2013

If it boot Xell, it is a smc config error. keep messing with the values until it boots, if it boots and get stuck at the Xbox logo, try another value for powermode. I also know that on a zephyr sometimes you have to use a falcon image, so if all else fails try building an image for a zephyr, even though this probably wont work, it is worth a try.

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R-JTAG Falcon boots xell but dash

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