Falcon R-JTAG...SMC rest limit issue...

[paulpsomiadis]

Console Type: Falcon
NAND size: 16
Dashboard version: 2.0.15574
CB version: 5774
Screenshot of NAND details from J-Runner:



J-Runner log:

===================================================
01 October 2013 23:44:19

J-Runner v0.3 Beta (2) Started



Checking Files
Finished Checking Files
Initializing orig_ms28.bin..
Falcon/Opus
Jtag Selected
Nand Initialization Finished
Aud_Clamp Selected
R-Jtag Selected
Load Files Initiliazation Finished
Clean SMC detected
Patching Jasper version 2.3 SMC at offset 0x12BA
16537
Started Creation of the 16537 xebuild image
KV Info saved to file
---------------------------------------------------------------
     xeBuild v1.09.639
---------------------------------------------------------------
base path changed to D:\xbox-tools\J-Runner\xeBuild
---- { Image Build Mode } ----
building jtag image


******* WARNING: could not patch SMC reset limit!

---------------------------------------------------------------
D:\xbox-tools\J-Runner\429273174505\updflash.bin image built, info:
---------------------------------------------------------------
Kernel    : 2.0.16537.0
Console   : Falcon
NAND size : 16MiB
Build     : JTAG
Xell      : power on console with console eject button
Serial    : 429273174505
ConsoleId : 029876104412
MoboSerial: 757857F225908335
Mfg Date  : 11/08/2007
CPU Key   : BE312D81D9FF8A8C9A26C3AAE454BACD
1BL Key   : DD88AD0C9ED669E7B56794FB68563EFA
DVD Key   : 46CD5C60D7ED145C311DD4CCC713DB88
CF LDV    : 14
KV type   : type2 (hashed - unchecked, master key not available)
---------------------------------------------------------------
    xeBuild Finished. Have a nice day.
---------------------------------------------------------------
Saved to D:\xbox-tools\J-Runner\429273174505
Image is Ready

POST output from J-Runner (either POST_OUT monitor or RATER output):

Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 01 
Post 01 
Post 22 - INIT_SECENG 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post DE 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 49 - SHA_VERIFY 
Post 4B - LZX_EXPAND 
Post 70 - INIT_VIDEO_DRIVER 
Post 0C 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Power Up
Waiting for POST to change
Post C0 
Post C0 
Post 22 - INIT_SECENG 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 20 - CB entry point reached 
Post 70 - INIT_VIDEO_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 87 - Panic - ALIGNMENT 
Post 70 - INIT_VIDEO_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 87 - Panic - ALIGNMENT 
Post 70 - INIT_VIDEO_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 87 - Panic - ALIGNMENT 
Post 70 - INIT_VIDEO_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 20 - CB entry point reached 
Post 70 - INIT_VIDEO_DRIVER 
Post 40 - Entrypoint of CD reached 
Post 70 - INIT_VIDEO_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Most Fails(cumulative): 0x22
Shutdown

Images



Description of problem: Console boots Xell flawlessly every time after about 3-4 glitches, but cannot patch SMC reset limit in J-Runner and this means cannot boot retail dash reliably
(I have seen it boot once or twice, so it does work - also boots reliably with RATER plugged in...but sometimes after 7-9 glitches, which it cannot get to as it usually stops after 5 glitches when the RATER is unplugged and the R-JTAG is standalone)

Was the console working before you started: Y

Basically my issue is that although my install is fine, I cannot get to retail dash reliably...

I saw on THIS thread that there was a guy with a similar issue, but I cannot download the pre-patched SMC.bin you guys provided to him (links are dead).

http://team-xecuter.com/forums/showthread.php/136622-Can-t-patch-SMC-reset-limit-R-JTAG

This is my ONLY issue - and I'm pleased as pop with the R-JTAG...totally ace product!

Just hope you guys can help out a fellow modder...

(@admin - could you please remove the picture with the CPU key still on...that was posted in error...)

 

[Martin C]

That error has nothing to do with your console only booting 'sometimes'.

we need pics.

 

[paulpsomiadis]

added images to original post as requested...

 

[Martin C]

You've got it set to DIP 1:


Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 87 - Panic - ALIGNMENT

This normally indicates it's just 'missing'

Have you tried DIP 2?

 

[paulpsomiadis]

DIP 2 seems to boot Xell at about the same glitch rate 3-4 glitches...

Can't remember what it did for the retail dash, as it's been a while since I put the console back together...

Will give it a shot in the morning, as it's 2:00am here now...

Is there anywhere I can read up on what the RATER output all means? I'd like to interpret results on the fly myself if possible...

 

[Martin C]

There's more detail about POST in the R-JTAG installation and tuning guide.

 

[paulpsomiadis]

Power Up
Waiting for POST to change
Post F2 - Panic - SHA_VERIFY_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 49 - SHA_VERIFY 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 70 - INIT_VIDEO_DRIVER 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post C0 
Post 12 - FSB_CONFIG_RX_STATE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Power Up
Waiting for POST to change
Post F2 - Panic - SHA_VERIFY_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post C0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post C0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post C0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post C0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post 12 - FSB_CONFIG_RX_STATE 
Post 15 - FETCH_OFFSET 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 60 - INIT_KERNEL 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post C0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post C0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post C0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 15 - FETCH_OFFSET 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Reached No. of Boots Required

...Yeah, I'd say that DIP 2 might be a bit better at booting...Heheheh, LOL!

I'm guessing RATER does a Xell boot, as that's what I'm observing on my LCD monitor output from the X360.

As for this:

Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post C0

Is this normal, or does it indicate another issue like a QSB point that has de-soldered / come un-stuck?

Also, it STILL won't boot to retail dash reliably...usually just stops glitching and nothing...

Seems to be getting stuck initializing video on "normal" boot...

Version: 10
Press Escape to exit
Waiting for POST to change
Post 10 - Payload/1BL started
Post 22 - INIT_SECENG
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post C0
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post E0
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post E0
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post E0
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post C0
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post C0
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post E0
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post E0
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post C0
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post E0
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post C0
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post C0
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 23 - INIT_SYSRAM
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 3B - PCI_INIT
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4D - DECODE_FUSES
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS
Post 5F
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 6C - INIT_SECURITY
Post 6D - INIT_KEY_EX_VAULT
Post 6E - INIT_SETTINGS
Post 6F - INIT_POWER_MODE
Post 70 - INIT_VIDEO_DRIVER

 

[Martin C]

It's normal to see a little 'junk' at the start of POST, but you might want to change the R-JTAG power mode to something else if you're getting situations where it just hangs.

 

[paulpsomiadis]

Currently using 1.2V...will try STANDARD and 1.8V and report back...:cool2:

 

[paulpsomiadis]

Well, it's case closed - just not the way I hoped...seems that the mainboard was faulty...:facepalm:

It just stopped powering on!:crazy:

Even re-flashed stock nand and removed all mods...NOTHING!

Ah well...at least I still have my R-JTAG kit and programmer for another mainboard...

 

[xboxhack11]

It is OK to admit you monkeyed up the main board.

You are among friends (as you claim it worked in your template).

 

[paulpsomiadis]

As you guys can see, my soldering was spot-on...no idea what goosed the mainboard...but It was just an experiment anyhow...already have my stable RGH2 Trinity anyways...

Still, a bit of X360 tinkering now and then keeps your edges sharp...