falcon r jtag wont boot

shawndezy115 · Aug 25, 2013

Console Type: Falcon
NAND size: 16
Dashboard version: 16202
CB version: IDK
Screenshot of NAND details from J-Runner:
(attach an image to your post)
J-Runner log:
POST output from J-Runner (either POST_OUT monitor or RATER output):
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 10 - Payload/1BL started
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 60 - INIT_KERNEL
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 60 - INIT_KERNEL
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 60 - INIT_KERNEL
Post 30 - VERIFY_OFFSET_4BL_CD
Post 60 - INIT_KERNEL
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 12 - FSB_CONFIG_RX_STATE
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 12 - FSB_CONFIG_RX_STATE
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 12 - FSB_CONFIG_RX_STATE
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 12 - FSB_CONFIG_RX_STATE
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 70 - INIT_VIDEO_DRIVER
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 30 - VERIFY_OFFSET_4BL_CD
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Most Fails(cumulative): 0xA0
Shutdown

Image of R-JTAG board: will post later
Images of close-up soldering to motherboard:
(attach images to your post)

Description of problem:wont boot

Was the console working before you started: Y

if i revert back to stock it works just fine.

idk what the post out means.
and i keep getting Post A0 - Panic - VERIFY_SECOTP_6 no matter what. i have checked all points. and tried both top and bottom RST points.

this is my first rjtag so take it easy on me.

scott1503 · Aug 25, 2013

Fill out the rest of the template please

gavin_darkglide · Aug 26, 2013

I had a falcon that did this exact same thing, no matter what settings i tried....... I ended up removing r-jtag, and selling it as a stock board, went and picked up another falcon and it worked........ If you want to fix it i would think the cpu needs reflowed...... dont quote me, just a guess considering that you havnt followed the standard template with pictures and everything.

scott1503 · Aug 26, 2013

gavin_darkglide said:
I had a falcon that did this exact same thing, no matter what settings i tried....... I ended up removing r-jtag, and selling it as a stock board, went and picked up another falcon and it worked........ If you want to fix it i would think the cpu needs reflowed...... dont quote me, just a guess considering that you havnt followed the standard template with pictures and everything.

Why guess when it could be a stab in the dark we really need pictures before we can say anything unless any one like Martin is around who will understand the rater more

shawndezy115 · Aug 26, 2013

Screen Shot 2013-08-25 at 8.36.39 PM.png

these are the best i could get. let me know if you want me to try again.
ps my work looks like sh*t up close. lol

currently set dips are just 7.
have tried 3-5 and 7

tried cleaning up. but still no luck.
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 60 - INIT_KERNEL
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 10 - Payload/1BL started
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post B0 - Panic - VERIFY_CONSOLE_TYPE
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 10 - Payload/1BL started
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 70 - INIT_VIDEO_DRIVER
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post E0
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 60 - INIT_KERNEL
Post 20 - CB entry point reached
Post 60 - INIT_KERNEL
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Most Fails(cumulative): 0xA0
Shutdown

shawndezy115 · Aug 26, 2013

CLEANED UP BACK QSBS AND STILL NO GO.
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 60 - INIT_KERNEL
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 70 - INIT_VIDEO_DRIVER
Post 12 - FSB_CONFIG_RX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 10 - Payload/1BL started
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 12 - FSB_CONFIG_RX_STATE
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 10 - Payload/1BL started
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 60 - INIT_KERNEL
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 40 - Entrypoint of CD reached
Most Fails(cumulative): 0xA0
Shutdown

scott1503 · Aug 26, 2013

Clean up the points again get as much of the massive balls of solder of those points and move the CPU rst (blue wire ) to the correct point try this one.
and have you tried every dip setting and every voltage ?

Taijigamer2 · Aug 26, 2013

Your POST qsb looks a bit rough. Are u using flux. Try applying some flux to the qsb and touching up the points, always clean afterwards with Iso alcohol. Your cpu_rst wire should be soldered to R8C2.

You didn't need to solder stby_clk for RJtag but leave it because messing up that point brings a whole new level of issues. Your v3 qsb looks a bit overloaded with solder and u may have bridged E & F underneath. Try touching up with flux, if still no joy, try removing it and reinstalling it, be careful of stby_clk. good luck

- - - Updated - - -

scott1503 said:
Clean up the points again get as much of the massive balls of solder of those points and move the CPU rst (blue wire ) to the correct point try this one.
and have you tried every dip setting and every voltage ?

Lol, beat me to it :smile:

Martin C · Aug 26, 2013

POST looks ok. There are 18 combinations which need to be tested before even starting a thread.

shawndezy115 · Aug 26, 2013

Im sorry martin. but i keep getting the "Most Fails(cumulative): 0xA0"
in the instruction stick it says if you get it there is something wrong with installation.
I will try more dip combos and settings. i did not change the voltage or anything yet. i thought they where for tuning. figured it would have booted at least once with basic settings.

thanks for the help.
like I said first time using Rjtag and rater.

scott1503 · Aug 26, 2013

shawndezy115 said:
Im sorry martin. but i keep getting the "Most Fails(cumulative): 0xA0"
in the instruction stick it says if you get it there is something wrong with installation.
I will try more dip combos and settings. i did not change the voltage or anything yet. i thought they where for tuning. figured it would have booted at least once with basic settings.

thanks for the help.
like I said first time using Rjtag and rater.

Did you not even notice my comment ! Your CPU rst is in the wrong place move it to the right place then start the dips

rdubbs007 · Aug 26, 2013

scott1503 said:
Did you not even notice my comment ! Your CPU rst is in the wrong place move it to the right place then start the dips

LOL... THIS!

shawndezy115 · Aug 28, 2013

what a tale i have. so after listening to scott i moved my cable to the right spot. after checking all my points 20 times i held my iron to long on Rc82 and boom lifted the f**king cap.
on top of that i lost it in a glob of solder. luckly i have a bunch of RROD boxes in my basement.
got a cap from there and tried putting it in.
pulled off the pad. so i fixed the trace and installed.

after all this still no love.
so i removed the QSB near the chip and did a straight wire install.
still no love.
mesed with dips. still no love.
tried voltage. no love.
eventual replaced my red power wire and hit all the points on the chip with flux and reconnected all wires.
it booted. got cpu key. built image and wrote it.
it booted.
installed dvd drive and hd.
RROD
RROD
RROD
Boot
Boot
RROD
RROD.

so replacing all wires and having a wire going to both bottom and top CPU reset points i was able to trouble shoot and find which one worked best. and on what jumper.

i ended up on jumper 1,7 470 1.2v with aud clamp
getting a soled 10 on rater. all 20 boots where 1's.
calling it a night.
but happy i got it working.
very satisfied with both the Rjtag and the Rater.
no way i could have done it without it.
may upgrade a few of my buddies coolrunner revA chips to Rjtags now that i got it down. random boot times such.

Thanks all for the help.

mrdrifta · Aug 28, 2013

Just a heads up, its possible to remove the resistor from the alt CPU_RST point Martin_C has given and bridge the points with solder, then you can simply use the via on the header as you would on an RGH install.

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