Hi guys, I am having some trouble with getting a Jasper CR4 Demon install to boot. I have tested retail it boots fine, also flashed retail to demon it also boots fine. Now im trying to glitch the console.
My settings for xell were JTAG, with AUD_CLAMP, I wrote the xell and it failed to boot yet it trys to glitch with the debug light on.
Images:
http://imgur.com/xs7G4wk
http://imgur.com/tA7PaOE
http://imgur.com/PuS6PcI
http://imgur.com/v6v9Z9N
http://imgur.com/fC6IqHT
Here are is my JRunner log along with rater output.
Checking Files
Jtag Selected
Finished Checking Files
Aud_Clamp Selected
Initializing nanddump1.bin..
Jasper 16MB
Nand Initialization Finished
DEMON
Hardware : Demon Phat
Firmware : 1.0
Flash ID : 0x73AD Hynix (16MiB - Small block)
Flash Size : 0x400 blocks of 0x4200 bytes
Writing Nand
Done!
in 0:34 min:sec
XeLL file created Successfully jasper_hack_aud_clamp.bin
DEMON
Hardware : Demon Phat
Firmware : 1.0
Flash ID : 0x73AD Hynix (16MiB - Small block)
Flash Size : 0x400 blocks of 0x4200 bytes
Writing Nand
Done!
in 0:03 min:sec
Version: 10
Press Escape to exit
Waiting for POST to change
Post 05
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 0E
Post 0F
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 0E
Post 0F
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 0E
Post 0F
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 0E
Post 0F
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 0E
Post 0F
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 0E
Post 0F
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 26 - FETCH_HEADER_3BL_CC
Post 27 - VERIFY_HEADER_3BL_CC
Post 28 - FETCH_CONTENTS_3BL_CC
Post 29 - HMACSHA_COMPUTE_3BL_CC
Post 2B - RC4_DECRYPT_3BL_CC
Post 2C - SHA_COMPUTE_3BL_CC
Post 2D - SIG_VERIFY_3BL_CC
Post 2E - HWINIT
Post 2F - RELOCATE
Post 30 - VERIFY_OFFSET_4BL_CD
Post 31 - FETCH_HEADER_4BL_CD
Post 32 - VERIFY_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 38 - SIG_VERIFY_4BL_CD
Post 3F
Post 01
Could anyone point me in the right direction?
My settings for xell were JTAG, with AUD_CLAMP, I wrote the xell and it failed to boot yet it trys to glitch with the debug light on.
Images:
http://imgur.com/xs7G4wk
http://imgur.com/tA7PaOE
http://imgur.com/PuS6PcI
http://imgur.com/v6v9Z9N
http://imgur.com/fC6IqHT
Here are is my JRunner log along with rater output.
Checking Files
Jtag Selected
Finished Checking Files
Aud_Clamp Selected
Initializing nanddump1.bin..
Jasper 16MB
Nand Initialization Finished
DEMON
Hardware : Demon Phat
Firmware : 1.0
Flash ID : 0x73AD Hynix (16MiB - Small block)
Flash Size : 0x400 blocks of 0x4200 bytes
Writing Nand
Done!
in 0:34 min:sec
XeLL file created Successfully jasper_hack_aud_clamp.bin
DEMON
Hardware : Demon Phat
Firmware : 1.0
Flash ID : 0x73AD Hynix (16MiB - Small block)
Flash Size : 0x400 blocks of 0x4200 bytes
Writing Nand
Done!
in 0:03 min:sec
Version: 10
Press Escape to exit
Waiting for POST to change
Post 05
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 0E
Post 0F
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 0E
Post 0F
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 0E
Post 0F
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 0E
Post 0F
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 0E
Post 0F
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 0E
Post 0F
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 26 - FETCH_HEADER_3BL_CC
Post 27 - VERIFY_HEADER_3BL_CC
Post 28 - FETCH_CONTENTS_3BL_CC
Post 29 - HMACSHA_COMPUTE_3BL_CC
Post 2B - RC4_DECRYPT_3BL_CC
Post 2C - SHA_COMPUTE_3BL_CC
Post 2D - SIG_VERIFY_3BL_CC
Post 2E - HWINIT
Post 2F - RELOCATE
Post 30 - VERIFY_OFFSET_4BL_CD
Post 31 - FETCH_HEADER_4BL_CD
Post 32 - VERIFY_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 38 - SIG_VERIFY_4BL_CD
Post 3F
Post 01
Could anyone point me in the right direction?
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