JTAG Jasper 16mb R-JTAG Xell Booting problems HELP!

Taijigamer2 · Oct 12, 2013

The AUD clamp is part of the jtag qsb. Sorry there was a way to take a post log of a stock boot. Best ask someone with more experience. Also read the r-jtag tutorial on this site as it has clear pics and instructions. Always use flux when soldering and clean your points afterwards with isopropyl alcohol to clean up any resudue. Good luck.

jsinger47 · Oct 12, 2013

Taijigamer2 said:
The AUD clamp is part of the jtag qsb. Sorry there was a way to take a post log of a stock boot. Best ask someone with more experience. Also read the r-jtag tutorial on this site as it has clear pics and instructions. Always use flux when soldering and clean your points afterwards with isopropyl alcohol to clean up any resudue. Good luck.

How to monitor POST.

1. Don't touch the JTAG QSB. It doesn't affect stock.
2. Turn all dips on CR/RJTAG off.

BAM! Post monitor.

Pokeastuff · Oct 12, 2013

Thanks! Lol It's doing perfect boots... "All dips are on"

Code:

Phat Selected
Version: 10
Power Up
Waiting for POST to change
Shutdown
Power Up
Waiting for POST to change
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Shutdown
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Shutdown
Power Up
Waiting for POST to change
Post 1E - BRANCH 
Post 1E - BRANCH 
Post 1A - RC4_INITIALIZE 
Post 1E - BRANCH 
Post 1A - RC4_INITIALIZE 
Post 1A - RC4_INITIALIZE 
Post 1A - RC4_INITIALIZE 
Post 1E - BRANCH 
Post 1E - BRANCH 
Post 1A - RC4_INITIALIZE 
Post 0A 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Shutdown
Power Up
Waiting for POST to change
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Shutdown
Resetting................

jsinger47 · Oct 12, 2013

Pokeastuff said:

Thanks! Lol It's doing perfect boots... "All dips are on"

Code:

Phat Selected
Version: 10
Power Up
Waiting for POST to change
Shutdown
Power Up
Waiting for POST to change
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Shutdown
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Shutdown
Power Up
Waiting for POST to change
Post 1E - BRANCH 
Post 1E - BRANCH 
Post 1A - RC4_INITIALIZE 
Post 1E - BRANCH 
Post 1A - RC4_INITIALIZE 
Post 1A - RC4_INITIALIZE 
Post 1A - RC4_INITIALIZE 
Post 1E - BRANCH 
Post 1E - BRANCH 
Post 1A - RC4_INITIALIZE 
Post 0A 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Shutdown
Power Up
Waiting for POST to change
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 06 
Post 1E - BRANCH 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Shutdown
Resetting................

Not sure why you'd turn all the dips "on" when i said to turn them "off."

chase · Oct 12, 2013

i believe he meant all dips off.. also, that post output doesn't look right for stock boot..

edit: I guess i'm just too slow today

Pokeastuff · Oct 12, 2013

Sorry didn't understand. Looks the same to me though "All Dips are off".

Code:

Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 0A 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Shutdown
Power Up
Waiting for POST to change
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 07 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Shutdown
Power Up
Waiting for POST to change
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Shutdown
Power Up
Waiting for POST to change
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Shutdown
Power Up
Waiting for POST to change
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 12 - FSB_CONFIG_RX_STATE 
Post 03 
Post 01 
Post 31 - FETCH_HEADER_4BL_CD 
Post 01 
Post 31 - FETCH_HEADER_4BL_CD 
Post 01 
Post 31 - FETCH_HEADER_4BL_CD 
Post 01 
Post 31 - FETCH_HEADER_4BL_CD 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Shutdown
Power Up
Waiting for POST to change
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 16 - FETCH_HEADER 
Post 06 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 03 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Shutdown
Resetting................

Taijigamer2 · Oct 12, 2013

I may be wrong (and it wouldn't be the first time today

) but that post log doesn't look right. It should go in sequence, 01 through to 79, seems to be missing bits. Please post pics of your post qsb soldering.

jsinger47 · Oct 12, 2013

Taijigamer2 said:
I may be wrong (and it wouldn't be the first time today ) but that post log doesn't look right. It should go in sequence, 01 through to 79, seems to be missing bits. Please post pics of your post qsb soldering.

Yes, you are wrong.

Stock NANDs don't do POST out for the important parts of the boot sequence anymore. I forget which dash update did this.

jsinger47 · Oct 12, 2013

In this thread, POST #34 had completely fine POST output. He even had a full boot from 10 to 79. Why did anyone recommend changing anything?

Pokeastuff · Oct 12, 2013

Haha it's okay, I really appreciate the help!!

jsinger47 · Oct 13, 2013

Yeah, your POST soldering there does need some work.

You have some really dry points.

Flux is a necessity.

Pokeastuff · Oct 13, 2013

Okay, should that fix the problems?

jsinger47 · Oct 13, 2013

Pokeastuff said:
Okay, should that fix the problems?

Maybe, provided that the rest of your solder work is competent.

Pokeastuff · Oct 13, 2013

Lol alright thanks, I`ll run out and get some tomorrow.

Taijigamer2 · Oct 13, 2013

At least u've established that your post qsb is working. As jsinger47 said, u need to touch up your points with flux, try to get no-clean flux ( superflux is great if u can get it). Tidy up all of your points and then clean with isopropyl alcohol. As jsinger said, u had a successful boot in post#34, completely missed that :facepalm:. Now u just need to tidy everything up and experiment with the settings to get a fast booting jtag

Pokeastuff · Oct 13, 2013

I got the Flux, soldered the points again. They look great. Went to solder the CPU_RST again to make sure it was connected and it came off. Tried to get it back on.... but in the end I can't find it now... Is there anything I can do to fix this? It won't turn on

jsinger47 · Oct 13, 2013

Pics please

In the case of a spelling error, I blame Tapatalk.

Pokeastuff · Oct 13, 2013

jsinger47 · Oct 13, 2013

Just bridge those two pads and solder the wire to J8C2

Pokeastuff · Oct 14, 2013

Okay thanks, Sorry do you mean J8C1? I can't find a J8C2

Search

Search

JTAG Jasper 16mb R-JTAG Xell Booting problems HELP!

Taijigamer2

jsinger47

Pokeastuff

Full Member

jsinger47

chase

Pokeastuff

Full Member

Taijigamer2

jsinger47

jsinger47

Pokeastuff

Full Member

jsinger47

Pokeastuff

Full Member

jsinger47

Pokeastuff

Full Member

Taijigamer2

Pokeastuff

Full Member

jsinger47

Pokeastuff

Full Member

jsinger47

Pokeastuff

Full Member