Jasper 512Mo - Xell wont boot - ROD 0010

Zou

Zou

Noob Account
Apr 26, 2005
7
0
Belgium
[SOLVED] Jasper 512Mo - Xell wont boot - ROD 0010

Hi all,

Console Type: Jasper
NAND size: 512
Dashboard version: 2.0.16203
CB version: 6754
Screenshot of NAND details from J-Runner:
Jrunner.jpg
J-Runner log:
Code: 
===================================================
mercredi 27 novembre 2013 17:59:59

J-Runner v0.3 Beta (3) Started


WARNING! - Your selected working directory already contains files!
You can view these files by using 'Show Working Folder' Button


Checking Files
Finished Checking Files
Initializing nanddump1.bin..
Jasper BB
Jtag Selected
Nand Initialization Finished
Comparing...Takes a while on big nands
Nands are the same
Aud_Clamp Selected
R-Jtag Selected
Jasper 512MB Manually Selected
Patching Jasper version 2.3 SMC at offset 0x12BA
XeLL file created Successfully jasper_hack_bigblock_aud_clamp.bin
Version: 10
Flash Config: 0x00AA3020
Writing Nand
jasper_hack_bigblock_aud_clamp.bin
Done!
in 0:18 min:sec
POST output from J-Runner (either POST_OUT monitor or RATER output):

RJtag 1.1 config : 1/7/8 ON | 1.8V
Code: 
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 98 - Panic - NEXT_STAGE_SIZE 
Post 18 - FETCH_CONTENTS 
Post 08 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 01 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 60 - INIT_KERNEL 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post E0 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 01 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 01 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 60 - INIT_KERNEL 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 70 - INIT_VIDEO_DRIVER 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post F6 
Post B6 - Panic - DECODE_FUSES 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 26 - FETCH_HEADER_3BL_CC 
Post 22 - INIT_SECENG 
Post 20 - CB entry point reached 
TIMEOUT or SMC CORRUPTED - Shutting Down
Shutdown
Power Up
Waiting for POST to change
TIMEOUT or SMC CORRUPTED - Shutting Down
Shutdown
RJtag 1.1 config : 1/7/8 ON | 1.8V
Code: 
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 18 - FETCH_CONTENTS 
Post 08 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post E0 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 01 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 60 - INIT_KERNEL 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 20 - CB entry point reached 
Post 60 - INIT_KERNEL 
Post 20 - CB entry point reached 
Post F7 
Post B2 - Panic - VERIFY_HEADER 
Post 32 - VERIFY_HEADER_4BL_CD 
Post 20 - CB entry point reached 
Most Fails(cumulative): 0xA0
Shutdown
Image of R-JTAG board:
RJTAG1.1.jpgJ2B1.jpgCPU_RST.jpgPOST_OUT.jpgJTAG.jpgAUD_CLAMP.jpg

Description of problem:

Dumped nand 2 times -> Ok same
Created Xell-Realoaded -> Ok
Write Xell -> OK
Trying to boot -> all seems ok at begining. Green light till I got a ROD, trying different config (CPU_RSt uperside/downside MB, tested different DIP, ...). Sometime I got ROD (err. 0010) after 1 cycle some times after 6 cycles. Its like the chip working fine but Xell-Reload is'nt good.
I restore original dump and the console boot without a prob (All wired still soldered except the +5V)

Was the console working before you started: Yes
 
Last edited:
C

charincol

VIP Member
Sep 5, 2011
152
0
Colorado
The original JTAG wiring uses a straight wire between points 4 and 7 at J2D2. You've got a diode there. Try swapping for a straight wire.
 
Zou

Zou

Noob Account
Apr 26, 2005
7
0
Belgium
Thx for your reply.

True but this mod is more secure, I alway used this wiring for Jtag (and for RJtag) without problem.

Anyway, when i waited for answer I continue testing the rater mode and I got Xell (after 10 tries) with the same RJtag config.

Actually I installed only 2 RJtag before and I never had encountered this kind of situation.

I'll continue testing to have the best booting time.
 
C

charincol

VIP Member
Sep 5, 2011
152
0
Colorado
Some Voltage/DIP/Res combos will give you RROD errors no matter what. It's really not an issue. That's why you need to try every combo available. I've gone thru all 200+ combos on a stubborn Jasper before.
 
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Zou

Zou

Noob Account
Apr 26, 2005
7
0
Belgium
charincol said:
Some Voltage/DIP/Res combos will give you RROD errors no matter what. It's really not an issue. That's why you need to try every combo available. I've gone thru all 200+ combos on a stubborn Jasper before.
Click to expand...
Yup, that's what I did not know

Edit:

Ok, i think I got the best result :
Aud_Clamp wiring
DIP 4/7/8 ON
1.2V
CPU_RST Upperside

With this i got 100% boot on 20 tries (75% 1st cycle, 25% 2 cycles) ... what else?
 
Last edited:
Martin C

Martin C

VIP Member
Jan 10, 2004
35,981
0
Scotland, UK
www.team-xecuter.com
charincol said:
Some Voltage/DIP/Res combos will give you RROD errors no matter what. It's really not an issue. That's why you need to try every combo available. I've gone thru all 200+ combos on a stubborn Jasper before.
Click to expand...
There are 18 combinations. I have no idea where 200+ comes from.
 
C

charincol

VIP Member
Sep 5, 2011
152
0
Colorado
Martin C said:
There are 18 combinations. I have no idea where 200+ comes from.
Click to expand...
3 voltages x 6 DIP x 3 res values x 2 Aud Clamp ON/OFF = 108 different combos with hardware. Then throw in different soldering locations for CPU_RST (can change results) so there you have it. Sorry to get so technical but aren't we all a bunch of technical geeks?
 
Martin C

Martin C

VIP Member
Jan 10, 2004
35,981
0
Scotland, UK
www.team-xecuter.com
charincol said:
3 voltages x 6 DIP x 3 res values x 2 Aud Clamp ON/OFF = 108 different combos with hardware. Then throw in different soldering locations for CPU_RST (can change results) so there you have it. Sorry to get so technical but aren't we all a bunch of technical geeks?
Click to expand...
Since the JTAG wiring comes to play AFTER POST 2E, it's moot. AUD_CLAMP is depending on your image type, so is also moot.

Like I said, 18 combinations. If you don't know how to troubleshoot an R-JTAG installation, you're just better to ask. The information is freely available.
 
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