R-JTAG Jasper stuck at POST 6F INIT_POWER_MODE....does not boot to Xell!!!!!

M

MrKronic

Full Member
Jun 2, 2013
70
0
Console Type: Jasper
NAND size: 512MB
Dashboard version: e.g 2.0.16747
CB version: e.g 6754
Screenshot of NAND details from J-Runner:
NANDdetia.PNG
J-Runner log:
Code: 
[B][B][B][B][B][B]===================================================
[/B][/B][/B][/B][/B][/B]Saturday, May 03, 2014 3:21:17 PM


J-Runner v0.3 Beta (4) Started






Checking Files
Finished Checking Files
Initializing nanddump1.bin..
Jasper BB
Jtag Selected
Nand Initialization Finished
Comparing...Takes a while on big nands
Nands are the same
Checking Console..
Version: 10
Flash Config: 0x00AA3020
00AA3020
Jasper 512MB
CB Version: 6723
Aud_Clamp Selected
R-Jtag Selected
Patching Jasper version 2.3 SMC at offset 0x12BA
XeLL file created Successfully jasper_hack_bigblock_aud_clamp.bin
POST output from J-Runner (either POST_OUT monitor or RATER output):
Code: 
[B][B][B][B][B][B]Version: 10
Press Escape to exit
Waiting for POST to change
Post 40 - Entrypoint of CD reached
Post 44 - FETCH_CONTENTS
Post 4C - SWEEP_CACHES
Post 0C
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 40 - Entrypoint of CD reached
Post 44 - FETCH_CONTENTS
Post 4C - SWEEP_CACHES
Post 0C
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 42 - FETCH_HEADER
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 6C - INIT_SECURITY
Post 6D - INIT_KEY_EX_VAULT
Post 6E - INIT_SETTINGS
Post 6F - INIT_POWER_MODE
Done!
[/B][/B][/B][/B][/B][/B]

Image of R-JTAG board:
IMG_20140503_131710.jpg
Images of close-up soldering to motherboard:
IMG_20140503_161759.jpgIMG_20140503_131645.jpgIMG_20140503_131531.jpgIMG_20140503_131450.jpg

Description of problem: I have recently started to do R-JTAG chips installations on xbox, starting with my own console. Its a Jasper 512mb box. So far, everything has gone fairly smooth, except when I try to boot into Xell. The console itself glitches correctly (since it can go past POST 0x2E) however it keeps getting stuck at POST 0x6F. I have pretty much tried all dip settings at different resistances to no avail and also carried out the checks to perform if the POST values are able to pass 2E (passed all of them). The setting at which the board glitches is at OFF resistance, with Dip settings 7-8-4.

I don't know whether this is significant, but I had to reflash Xell twice because I flashed the wrong image the first time, which did not have the RJTAG/AUD clamp settings selected(I'm trying to use the AUD clamp method). Please Help!!!!

Was the console working before you started: Yes
 

Attachments

M

MrKronic

Full Member
Jun 2, 2013
70
0
Taijigamer2 said:
Failure at POST 6x usually suggests jtag wiring/soldering. Check/reflow the points on your jtag qsb and check for continuity. Also 470ohm setting works well for jasper. Use Martin C's jtag guide for reference.

http://team-xecuter.com/forums/showthread.php?t=143908
Click to expand...
Tried all of the stuff mentioned in that thread....... Solution no. 3 checks out, and so does No. 2 (shows continuity at the corresponding points and the appropriate resistance in the jumper linked points) but not sure whether that means my soldering is alright... As for No.1, I'm using AUD clamp with all the appropriate settings, so if there is any other thing i missed, please feel free to point it out :)
 
M

MrKronic

Full Member
Jun 2, 2013
70
0
Also, the console seems to glitch at two different resistor settings...... It glitches consistently with the 3 way resistor switch set to OFF and with dip settings 8-7-4. It occasionally glitches when the resistance is set to 470 ohms and dips 8-7-4, however that's more like 1 glitch in 15-20 cycles.
 
M

MrKronic

Full Member
Jun 2, 2013
70
0
Yes it was. But I managed to solve the issue :D Seems that the 470ohm/ Dip combo 8-7-4/5 is doing the glitch perfectly after all. I figure the reason may be because I had the incorrect Xell image flashed at that time (the r-jtag/aud clamp options were auto-deselected when building the Xell image).

Thanks a lot anyway.... Please close this thread as being solved....
 
Last edited:
You must log in or register to reply here.