FIXED Little advice on R-Jtag Falcon

xzanox

VIP Member
Nov 1, 2011
905
48
Netherlands, 1336
{{{FIXED}}} READ LAST POST ON PAGE 1 FOR DETAILS!

Hi everybody, i finished this R-Jtag on a Falcon yesterday, but still have sometimes freezing issues and need a little advice what to do best after reading several threads about this issue. I will fill in the template below to supply as much info i can.

: First i would like to know if this can be solved by changing the cpu-rst wire a little more to the x-clamps or does this not affect that much and should i better straight away edit my smc settings to a different power mode? Here is the template:

Console Type:
Falcon
NAND size: 16
Dashboard version: 2.0.16203
CB version: e.g 5774
Screenshot of NAND details from J-Runner:

Image of R-JTAG board: R-Jtag chip.jpg
Images of close-up soldering to motherboard: see below

Using aud_clamp wire, 3-1, selected default 470 on qsb, haven't used any voltage settings yet...

If a jrunner log is needed, I will post this too, not sure if I had to since r-jtag was successful so far expect for the freezing..

Description of problem: Sometimes freeze after 10-30 minutes

Was the console working before you started: Yes and still does. The rater log is from first time booting in xell.
Code:
Version: 10
Power Up
Waiting for POST to change
Post 7F 
Post 24 - VERIFY_OFFSET_3BL_CC 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 87 - Panic - ALIGNMENT 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 87 - Panic - ALIGNMENT 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 87 - Panic - ALIGNMENT 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 87 - Panic - ALIGNMENT 
Post C0 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 87 - Panic - ALIGNMENT 
Post 01 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 87 - Panic - ALIGNMENT 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 87 - Panic - ALIGNMENT 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 87 - Panic - ALIGNMENT 
Post 2C - SHA_COMPUTE_3BL_CC 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 87 - Panic - ALIGNMENT 
Post 60 - INIT_KERNEL 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 87 - Panic - ALIGNMENT 
Post C0 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Tip: Load the nand on source to have quicker results.
Scanning.....
LockDownValue is 15
CPU Key is 3A1239597289C2B9BFD6462CF45A369F
Initializing nanddump1.bin..
Finished
CpuKey is Correct
Added Key to Database
Nand Initialization Finished
Shutdown]
Code:
---------------------------------------------------------------
     xeBuild v1.07.561
---------------------------------------------------------------
building jtag image
<enter> key on completion suppressed
data directory overridden from command line to '.\xeBuild\16203\'
per build directory overridden from command line to 'xeBuild\data'
file name overridden from command line to 'G:\XBOX360 RGH SOFTWARE\J-Runner v02 Beta (288) Core Pack\J-Runner v02 Beta (288) Core Pack\307576782505\updflash.bin'
------ parsing user ini at '.\xeBuild\data\options.ini' ------
loading file...done!
pre-parsing and sanitizing
done!
User options.ini loaded, 0x1b0 bytes in memory
loading cpukey.txt from .\xeBuild\data\cpukey.txt
CPU Key set to: 0x3A1239597289C2B9BFD6462CF45A369F
setting 1blkey from ini: 0xDD88AD0C9ED669E7B56794FB68563EFA
1BL Key set to: 0xDD88AD0C9ED669E7B56794FB68563EFA sum: 0x983 (expects: 0x983)
xex Key set to: 0x20B185A59D28FDC340583FBB0896BF91 sum: 0x800 (expects: 0x800)
Using patchsmc option (ini file)
------ parsing ini at '.\xeBuild\16203\_jtag.ini' ------
ini version 16203
ini: label [falconbl] found
found (1) 'cb_5770.bin' crc: 0x3279f0d5
found (2) 'cd_5770.bin' crc: 0xd04e8927
found (3) 'ce_1888.bin' crc: 0xff9b60df
found (4) 'cf_4532.bin' crc: 0xd28ef722
found (5) 'cg_4532.bin' crc: 0x2530f8ce
found (6) 'cb_5771.bin' crc: 0x859140f0
found (7) 'cd_8453.bin' crc: 0x25e0acd0
found (8) 'cf_16203.bin' crc: 0xc4c27121
found (9) 'cg_16203.bin' crc: 0xcbb44eac
ini: label [flashfs] found
found (1) 'aac.xexp' crc: 0x62924e10
found (2) 'bootanim.xex' crc: 0xc8b660b2
found (3) 'createprofile.xex' crc: 0x9f6efee2
found (4) 'dash.xex' crc: 0x18ea6c7e
found (5) 'deviceselector.xex' crc: 0x75c32b5b
found (6) 'gamerprofile.xex' crc: 0xec9746f7
found (7) 'hud.xex' crc: 0xabf19107
found (8) 'huduiskin.xex' crc: 0xf3563a5c
found (9) 'mfgbootlauncher.xex' crc: 0x763c73fe
found (10) 'minimediaplayer.xex' crc: 0xda1d0a4a
found (11) 'nomni.xexp' crc: 0xaae9ad36
found (12) 'nomnifwk.xexp' crc: 0xb3c2c31b
found (13) 'nomnifwm.xexp' crc: 0xf69cf9fc
found (14) 'SegoeXbox-Light.xtt' crc: 0xe0ee6049
found (15) 'signin.xex' crc: 0xc1d7185d
found (16) 'updater.xex' crc: 0x19286110
found (17) 'vk.xex' crc: 0xefcbab82
found (18) 'xam.xex' crc: 0xf8db3557
found (19) 'xenonclatin.xtt' crc: 0xd5d17ff5
found (20) 'xenonclatin.xttp' crc: 0x7a507ad1
found (21) 'xenonjklatin.xtt' crc: 0xdde4a14c
found (22) 'xenonjklatin.xttp' crc: 0xe2adddfb
found (23) 'ximecore.xex' crc: 0xe85e813b
found (24) 'ximedic.xex' crc: 0x1d992bfb
found (25) 'ximedic.xexp' crc: 0xfb2bb58c
found (26) '..\launch.xex' crc: 0x00000000
found (27) '..\lhelper.xex' crc: 0x00000000
found (28) '..\launch.ini' crc: 0x00000000
ini: label [security] found
found (1) 'crl.bin' crc: 0x00000000
found (2) 'dae.bin' crc: 0x00000000
found (3) 'extended.bin' crc: 0x00000000
found (4) 'secdata.bin' crc: 0x00000000
------ ini parsing completed ------
output name overridden to: G:\XBOX360 RGH SOFTWARE\J-Runner v02 Beta (288) Core Pack\J-Runner v02 Beta (288) Core Pack\307576782505\updflash.bin

------ Checking .\xeBuild\data\nanddump.bin ------
.\xeBuild\data\nanddump.bin file size: 0x1080000
nanddump header checks passed OK!
Loading NAND dump (0x1080000 bytes)...done!
Detecting NAND controller type from dump data...
 NAND dump is from a small block machine
 NAND dump uses small block controller
parsing dump into user and spare...
done!
decrypting KeyVault at address 0x4000 of size 0x4000
keyvault decrypted OK, will use if no kv.bin is provided
decrypting SMC at address 0x1000 of size 0x3000
SMC decrypted OK, will use if no external smc.bin is provided
seeking smc config in dump...found at offset 0xf7c000! Using if no smc config is provided.
CF slot 0 decrypted ok LDV 0x0f Pairing: 0x698046
CF slot 1 decrypted ok LDV 0x0e Pairing: 0x698046
setting LDV from image to 15
setting pairing data from image to 0x698046
MobileB.dat found at page 0x3100, size 2048 (0x800) bytes
MobileC.dat found at page 0x3360, size 512 (0x200) bytes
MobileD.dat found at page 0x21c0, size 2048 (0x800) bytes
MobileE.dat found at page 0x33a0, size 2048 (0x800) bytes
Statistics.settings found at page 0x7bc0, size 4096 (0x1000) bytes
seeking FSRoot...fsroot found at page 0xb40 raw offset 0x173400
seeking security files...
crl.bin found in sector 0x96 size 0xa00...verified! Will use if external file not found.
dae.bin found in sector 0x8e size 0xde60...verified! Will use if external file not found.
extended.bin found in sector 0x10f size 0x4000...verified! Will use if external file not found.
secdata.bin found in sector 0x8c size 0x400...verified! Will use if external file not found.
done!
Writing initial header to flash image
------ loading system update container ------
.\xeBuild\16203\su20076000_00000000 found, loading...done!
 Read 0xb31000 bytes to memory
checking container integrity...
header seems valid, version [URL="tel:2.0.16203.00"]2.0.16203.00[/URL]
header hash is OK, checking content hashes...
content hashes seem OK, everything looks good!
extracted SUPD\xboxupd.bin (0x79a60 bytes)
decrypting SUPD\xboxupd.bin\CF_16203.bin (0x4560 bytes)...done!
decrypting SUPD\xboxupd.bin\CG_16203.bin (0x754f2 bytes)...done!
------ Loading bootloaders and required security files ------
could not read .\xeBuild\16203\bin\payload.bin, using built in payload (0x200 bytes)
reading .\xeBuild\data\SMC.bin (0x3000 bytes)
reset smc load address to 0x1000 size 0x3000
reading .\xeBuild\data\kv.bin failed, using kv.bin from nand dump
reading .\common\cb_5770.bin (0x8e40 bytes)
reading .\common\cd_5770.bin (0x56c0 bytes)
reading .\common\ce_1888.bin (0x5606a b pad 0x56070 b)
reading .\common\cf_4532.bin (0x44c0 bytes)
reading .\common\cg_4532.bin (0x2ef40 bytes)
extracted SUPD\xboxupd.bin\CF_16203.bin (0x4560 bytes)
extracted SUPD\xboxupd.bin\CG_16203.bin (0x754f2 bytes)
could not read .\xeBuild\16203\bin\freeboot.bin, using built in core (0xd80 bytes)
reading .\xeBuild\16203\bin\patches_falcon.bin (0x9a4 bytes)
reading .\xeBuild\data\xell-2f.bin (0x40000 bytes)
reading .\common\cb_5771.bin (0x9340 bytes)
reading .\common\cd_8453.bin (0x5780 bytes)
reading .\xeBuild\data\smc_config.bin failed, using smc_config.bin from nand dump
-------------------
checking smc_config
-------------------
extracting config
------------------
SMC config info:
------------------
Target temps: Cpu:  80øC Gpu:  75øC Edram:  78øC
Max temps   : Cpu: 100øC Gpu: 100øC Edram: 102øC
Cpu Fan     : (auto)
Gpu Fan     : (auto)
MAC Address : 00:1d:d8:5f:4f:a9
AVRegion    : 0x00000300 (PAL50)
GameRegion  : 0x02fe (PAL/EU)
DVDRegion   : 2
resetKey    : AALU
---------------------
Checking for smc config data patches
smc config was not patched
---------------------
done!
------ Encrypting and finalizing bootloaders ------
initializing random nonces
Fuse CPU Key set to: 0x3A1239597289C2B9BFD6462CF45A369F
Fuse CF LDV set to : 0xFFFFFFFFFFFFFFF00000000000000000
encoding payload.bin size 0x200 (JTAG)
patching payload.bin to load size 0xd80 (0x360 reps)
encoding SMC.bin size 0x3000 (JTAG)
SMC checksum: a6ee8b80
unknown SMC found, type: Jasper v4.1(2.03)
jtag hack found in smc.bin!
******* WARNING: could not patch SMC reset limit!
encoding kv.bin size 0x4000 (JTAG)
decrypted keyvault has been set for reference
encoding cb_5770.bin size 0x8e40 (JTAG)
CB 5770 seq 0x01050018 type: 0x01 cseq: 0x05 allow: 0x0018
 expected fuses:
 fuseset 00: C0FFFFFFFFFFFFFF
 fuseset 01: 0F0F0F0F0F0F0FF0
 fuseset 02: 0000F00000000000 (sequence)
 fuseset 02: 000F000000000000 (allow cseq 4)
 fuseset 02: 0000F00000000000 (allow cseq 5)
encoding cd_5770.bin size 0x56c0 (JTAG)
encoding ce_1888.bin size 0x56070 (JTAG)
encoding cf_4532.bin size 0x44c0 (JTAG)
encoding cg_4532.bin size 0x2ef40 (JTAG)
encoding cf_16203.bin size 0x4560 (JTAG)
encoding cg_16203.bin size 0x75500 (JTAG)
encoding freeboot.bin size 0xd80 (JTAG)
patching freeboot.bin with option mask 0x4 and kernel version string '16203'
Options set:
    - console DVD eject button is being used to start xell 
    - alternate xell button disabled
encoding patches_falcon.bin size 0x9a8 (JTAG)
encoding fuses.bin size 0x60 (JTAG)
encoding xell-2f.bin size 0x40000 (JTAG)
encoding cb_5771.bin size 0x9340 (JTAG)
CB 5771 seq 0x01070058 type: 0x01 cseq: 0x07 allow: 0x0058
 expected fuses:
 fuseset 00: C0FFFFFFFFFFFFFF
 fuseset 01: 0F0F0F0F0F0F0FF0
 fuseset 02: 000000F000000000 (sequence)
 fuseset 02: 000F000000000000 (allow cseq 4)
 fuseset 02: 0000F00000000000 (allow cseq 5)
 fuseset 02: 000000F000000000 (allow cseq 7)
encoding cd_8453.bin size 0x5780 (JTAG)
Virtual Fuses set to:
 fuseset 00: C0FFFFFFFFFFFFFF
 fuseset 01: 0F0F0F0F0F0F0FF0
 fuseset 02: 000000F000000000
 fuseset 03: 3A1239597289C2B9
 fuseset 04: 3A1239597289C2B9
 fuseset 05: BFD6462CF45A369F
 fuseset 06: BFD6462CF45A369F
 fuseset 07: FFFFFFFFFFFFFFF0
 fuseset 08: [URL="tel:0000000000000000"]0000000000000000[/URL]
 fuseset 09: [URL="tel:0000000000000000"]0000000000000000[/URL]
 fuseset 10: [URL="tel:0000000000000000"]0000000000000000[/URL]
 fuseset 11: [URL="tel:0000000000000000"]0000000000000000[/URL]
done!
------ Adding bootloaders to flash image ------
adding payload.bin at raw offset 0x00000200 len 0x200 (end 0x400)
adding SMC.bin at raw offset 0x00001000 len 0x3000 (end 0x4000)
adding kv.bin at raw offset 0x00004000 len 0x4000 (end 0x8000)
adding cb_5770.bin at raw offset 0x00008000 len 0x8e40 (end 0x10e40)
adding cd_5770.bin at raw offset 0x00010e40 len 0x56c0 (end 0x16500)
adding ce_1888.bin at raw offset 0x00016500 len 0x56070 (end 0x6c570)
adding cf_4532.bin at raw offset 0x00070000 len 0x44c0 (end 0x744c0)
adding cg_4532.bin at raw offset 0x000744c0 len 0x2ef40 (end 0x80000, rest in fs)
adding cf_16203.bin at raw offset 0x00080000 len 0x4560 (end 0x84560)
adding cg_16203.bin at raw offset 0x00084560 len 0x75500 (end 0x90000, rest in fs)
adding freeboot.bin at raw offset 0x00090000 len 0xd80 (end 0x90d80)
adding patches_falcon.bin at raw offset 0x00091000 len 0x9a8 (end 0x919a8)
adding fuses.bin at raw offset 0x00095000 len 0x60 (end 0x95060)
adding xell-2f.bin at raw offset 0x00095060 len 0x40000 (end 0xd5060)
adding cb_5771.bin at raw offset 0x000d5060 len 0x9340 (end 0xde3a0)
adding cd_8453.bin at raw offset 0x000de3a0 len 0x5780 (end 0xe3b20)
Fixing up FS table...done!
Writing zeropair CG patch slot overflow data to sysupdate.xexp1
 at raw offset 0xe4000 len 0x00023400 (end: 0x00107400)...done!
Writing target CG patch slot overflow data to sysupdate.xexp2
 at raw offset 0xe4000 len 0x00069a60 (end: 0x0014da60)...done!
------ adding 28 firmware files ------
extracted SUPD\aac.xexp (0x14000 bytes) (crc32: 0x62924e10 ini: 0x62924e10)
 adding as aac.xexp2 at raw offset 0x171a60 len 0x00014000 (end 0x00185a60)
extracted SUPD\bootanim.xex (0x61000 bytes) (crc32: 0xc8b660b2 ini: 0xc8b660b2)
 adding as bootanim.xex at raw offset 0x188000 len 0x00061000 (end 0x001e9000)
extracted SUPD\createprofile.xex (0xc000 bytes) (crc32: 0x9f6efee2 ini: 0x9f6efee2)
 adding as createprofile.xex at raw offset 0x1e9000 len 0x0000c000 (end 0x001f5000)
extracted SUPD\dash.xex (0x59c000 bytes) (crc32: 0x18ea6c7e ini: 0x18ea6c7e)
 adding as dash.xex at raw offset 0x1f8000 len 0x0059c000 (end 0x00794000)
extracted SUPD\deviceselector.xex (0xa000 bytes) (crc32: 0x75c32b5b ini: 0x75c32b5b)
 adding as deviceselector.xex at raw offset 0x794000 len 0x0000a000 (end 0x0079e000)
extracted SUPD\gamerprofile.xex (0x1b000 bytes) (crc32: 0xec9746f7 ini: 0xec9746f7)
 adding as gamerprofile.xex at raw offset 0x79e000 len 0x0001b000 (end 0x007b9000)
extracted SUPD\hud.xex (0x1d000 bytes) (crc32: 0xabf19107 ini: 0xabf19107)
 adding as hud.xex at raw offset 0x7bb000 len 0x0001d000 (end 0x007d8000)
extracted SUPD\huduiskin.xex (0x14000 bytes) (crc32: 0xf3563a5c ini: 0xf3563a5c)
 adding as huduiskin.xex at raw offset 0x7d9000 len 0x00014000 (end 0x007ed000)
extracted SUPD\mfgbootlauncher.xex (0x8000 bytes) (crc32: 0x763c73fe ini: 0x763c73fe)
 adding as mfgbootlauncher.xex at raw offset 0x7f0000 len 0x00008000 (end 0x007f8000)
extracted SUPD\minimediaplayer.xex (0xb000 bytes) (crc32: 0xda1d0a4a ini: 0xda1d0a4a)
 adding as minimediaplayer.xex at raw offset 0x7f8000 len 0x0000b000 (end 0x00803000)
extracted SUPD\nomni.xexp (0xe000 bytes) (crc32: 0xaae9ad36 ini: 0xaae9ad36)
 adding as nomni.xexp2 at raw offset 0x803000 len 0x0000e000 (end 0x00811000)
extracted SUPD\nomnifwk.xexp (0x2000 bytes) (crc32: 0xb3c2c31b ini: 0xb3c2c31b)
 adding as nomnifwk.xexp2 at raw offset 0x812000 len 0x00002000 (end 0x00814000)
extracted SUPD\nomnifwm.xexp (0x5000 bytes) (crc32: 0xf69cf9fc ini: 0xf69cf9fc)
 adding as nomnifwm.xexp2 at raw offset 0x816000 len 0x00005000 (end 0x0081b000)
extracted SUPD\SegoeXbox-Light.xtt (0x6000 bytes) (crc32: 0xe0ee6049 ini: 0xe0ee6049)
 adding as SegoeXbox-Light.xtt at raw offset 0x81d000 len 0x00006000 (end 0x00823000)
extracted SUPD\signin.xex (0x16000 bytes) (crc32: 0xc1d7185d ini: 0xc1d7185d)
 adding as signin.xex at raw offset 0x826000 len 0x00016000 (end 0x0083c000)
extracted SUPD\updater.xex (0x7000 bytes) (crc32: 0x19286110 ini: 0x19286110)
 adding as updater.xex at raw offset 0x83e000 len 0x00007000 (end 0x00845000)
extracted SUPD\vk.xex (0xb000 bytes) (crc32: 0xefcbab82 ini: 0xefcbab82)
 adding as vk.xex at raw offset 0x847000 len 0x0000b000 (end 0x00852000)
extracted SUPD\xam.xex (0x24f000 bytes) (crc32: 0xf8db3557 ini: 0xf8db3557)
 adding as xam.xex at raw offset 0x853000 len 0x0024f000 (end 0x00aa2000)
reading .\xeBuild\16203\xenonclatin.xtt (0x11b000 bytes) (crc32: 0xd5d17ff5 ini: 0xd5d17ff5)
 adding as xenonclatin.xtt at raw offset 0xaa3000 len 0x0011b000 (end 0x00bbe000)
extracted SUPD\xenonclatin.xttp (0x18000 bytes) (crc32: 0x7a507ad1 ini: 0x7a507ad1)
 adding as xenonclatin.xttp2 at raw offset 0xbbf000 len 0x00018000 (end 0x00bd7000)
reading .\xeBuild\16203\xenonjklatin.xtt (0x1a8000 bytes) (crc32: 0xdde4a14c ini: 0xdde4a14c)
 adding as xenonjklatin.xtt at raw offset 0xbd8000 len 0x001a8000 (end 0x00d80000)
extracted SUPD\xenonjklatin.xttp (0x7000 bytes) (crc32: 0xe2adddfb ini: 0xe2adddfb)
 adding as xenonjklatin.xttp2 at raw offset 0xd80000 len 0x00007000 (end 0x00d87000)
extracted SUPD\ximecore.xex (0x17000 bytes) (crc32: 0xe85e813b ini: 0xe85e813b)
 adding as ximecore.xex at raw offset 0xd87000 len 0x00017000 (end 0x00d9e000)
reading .\xeBuild\16203\ximedic.xex (0x90000 bytes) (crc32: 0x1d992bfb ini: 0x1d992bfb)
 adding as ximedic.xex at raw offset 0xd9f000 len 0x00090000 (end 0x00e2f000)
extracted SUPD\ximedic.xexp (0x2800 bytes) (crc32: 0xfb2bb58c ini: 0xfb2bb58c)
 adding as ximedic.xexp2 at raw offset 0xe30000 len 0x00002800 (end 0x00e32800)
reading .\xeBuild\16203\..\launch.xex (0xc800 bytes)
 adding as launch.xex at raw offset 0xe32800 len 0x0000c800 (end 0x00e3f000)
reading .\xeBuild\16203\..\lhelper.xex (0x6000 bytes)
 adding as lhelper.xex at raw offset 0xe40800 len 0x00006000 (end 0x00e46800)
***** could not read file '..\launch.ini', skipping *****
------ adding 4 security files ------
<- Processing crl.bin ->
reading .\xeBuild\data\crl.bin (0xa00 bytes)
crl appears crypted, attempting to decrypt with CPU key...failed! Trying alternate key...success!
 adding as crl.bin at raw offset 0xe4c000 len 0x00000a00 (end 0x00e4ca00)
<- Processing dae.bin ->
reading .\xeBuild\data\dae.bin (0xad30 bytes)
dae appears encrypted, attempting to decrypt with CPU key...failed! Attempting to decrypt with alternate key...
success!
 adding as dae.bin at raw offset 0xe50000 len 0x0000ad30 (end 0x00e5ad30)
<- Processing extended.bin ->
reading .\xeBuild\data\extended.bin (0x4000 bytes)
 adding as extended.bin at raw offset 0xe5c000 len 0x00004000 (end 0x00e60000)
<- Processing secdata.bin ->
reading .\xeBuild\data\secdata.bin (0x400 bytes)
 adding as secdata.bin at raw offset 0xe60000 len 0x00000400 (end 0x00e60400)
------ checking for Mobile*.dat ------
MobileB.dat found, adding from nanddump.bin
 adding MobileB.dat as type 0x31 at raw offset 0xe64000 len 0x800 (end 0xe64800)
MobileC.dat found, adding from nanddump.bin
 adding MobileC.dat as type 0x32 at raw offset 0xe68000 len 0x200 (end 0xe68200)
MobileD.dat found, adding from nanddump.bin
 adding MobileD.dat as type 0x33 at raw offset 0xe6c000 len 0x800 (end 0xe6c800)
MobileE.dat found, adding from nanddump.bin
 adding MobileE.dat as type 0x34 at raw offset 0xe70000 len 0x800 (end 0xe70800)
Statistics.settings found, adding from nanddump.bin
 adding Statistics.settings at raw offset 0xf78000 len 0x1000 (end 0xf79000)
------ adding smc_config.bin ------
adding smc config to offset 0x00f7c000, len 0x400
------ finalizing image ------
Fixing up empty FS block entries...done!
Writing FS table to image offset 0xe74000 len 0x4000 (end 0xe78000)...done!
calculating ECD bytes and assembling raw image...done!
writing file 'G:\XBOX360 RGH SOFTWARE\J-Runner v02 Beta (288) Core Pack\J-Runner v02 Beta (288) Core Pack\307576782505\updflash.bin' to disk...done!
G:\XBOX360 RGH SOFTWARE\J-Runner v02 Beta (288) Core Pack\J-Runner v02 Beta (288) Core Pack\307576782505\updflash.bin written OK
---------------------------------------------------------------
G:\XBOX360 RGH SOFTWARE\J-Runner v02 Beta (288) Core Pack\J-Runner v02 Beta (288) Core Pack\307576782505\updflash.bin image built, info:
---------------------------------------------------------------
Console   : Falcon
NAND size : 16MiB
Build     : JTAG
Xell      : power on console with console eject button
Serial    : [URL="tel:307576782505"]307576782505[/URL]
ConsoleId : [URL="tel:016671906972"]016671906972[/URL]
MoboSerial: [URL="tel:7578576130318245"]7578576130318245[/URL]
Mfg Date  : 06/16/2008
CPU Key   : 3A1239597289C2B9BFD6462CF45A369F
1BL Key   : DD88AD0C9ED669E7B56794FB68563EFA
DVD Key   : 2CF57533BBDC62B8DEBC0F551AE1CBD6
CF LDV    : 15
KV type   : type2 (hashed)
---------------------------------------------------------------
    xeBuild Finished. Have a nice day.
---------------------------------------------------------------
Has this something to do with my soldering or connections or wiring? Should i shorten wires, i am using the standard length blue wire. Edit: I just put the blue wire closer to the x-clamp but had freeze again in game after 10 minutes.

I also read somehwere (martin C) about xmplayer if that freezes it most likely is a smc setting that needs to be changed, but the noob i am in rgh and all, i could use some advice which xmplayer to download (is there a specific version for this test or not?), how to play/test on the R-Jtag (usb stick or copy to hdd?) and eventually how to edit my smc settings config.

From what i now understand i should try change smc settings from power mode 8480 (this is what it says now when my nanddump is loaded) to e.g. 8080 since i hear a lot of problems get solved using that setting. Than i just save it as updflash.bin and use nand reader to create and write a new hacked R-Jtag image? Edit: just changed the value to 8080 and saved changes. I've got now a nanddump edited.bin. How do I create a updflash_edited.bin now? By creating image with this edited NAND dump loaded? Guess so right??

Bare with me, i am open to learn and also to take critics. Thanks for reading. Btw i am using dip 6 and 7 on. Had some RROD with boot when using dip 3 or 2, but 6 works fine, rater score of 9.20. I am using the bottom cpu_rst point and haven' tried the alternate point on the topside since it was booting 1-2 glitches with no RROD. Like Martin C suggests in that quote, should I use the alt point topside for when it RRods even when it doesn't rrod and should i give this a go to prevent the freezing?
 

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AllyNerd

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Feb 25, 2013
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Honestly I would try all the settings, first trying the different voltage settings. I always go thru all the combinations unless I just get a flawless instaboot setting. Cpu_rst routing looks fine. If it still freezes after that you can change the power mode.
 
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xzanox

VIP Member
Nov 1, 2011
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Honestly I would try all the settings, first trying the different voltage settings. I always go thru all the combinations unless I just get a flawless instaboot setting. Cpu_rst routing looks fine. If it still freezes after that you can change the power mode.
Thank you, so the voltage settings can also effect the freezing or these only affect the booting times? Because booting is not the problem of this falcon, 1-2 glitches all the time. I mean I'm open to try it and definitely will, but just trying to gather information on what affects what and what not...

Btw Ally just in case i need to change the smc config, am I correct if I say:

-I edit/change value of power mode
-safe it-
-use the newly created nanddumpedited.bin to create new updflash.bin by creating new jtag image.
-write image with NAND-x

Correct?
 
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xzanox

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Nov 1, 2011
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Netherlands, 1336
Tried voltage 1.2 then boot times are horrible. tried voltage 1.8 then boots directly but still freeze in game after 15 minutes.

Edit: also tried alt point. Boot times get worse and freezes still occur after 10-20 min. Now trying again different dips or shouldn't I do this because my rater was 9.20 with dip 6. Does the alt cpu_rst point conflicts/alters the dip settings in any way?
 
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morinzo

VIP Member
Oct 28, 2005
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just did a falcon and this was the best settings for mine. 7 & 5 on, default voltage, aud clamp, 470
 

xzanox

VIP Member
Nov 1, 2011
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Netherlands, 1336
just did a falcon and this was the best settings for mine. 7 & 5 on, default voltage, aud clamp, 470
Exactly, those settings look almost like mine, expect I have dip 6-7 both on, default voltage, and clamp, 470 and it works like a charm, boots consistently 1-2 times...so that's not the big problem, I'm trying to figure out what causes the freezing since I was under the impression R-Jtag would take away lots of problems like freezing issues... At this moment I've almost tried everything what I can think off...

Rerouted cpu_rst wire underside and topside mobo, taped completely with and without electrical tape for interference, Over fan shroud, next to fans etc etc.
tried voltage 1.2 and 1.8
tried longer blue wire (from slim set) cut to different lengths.
Even tried different dips again, also with different voltage etc no success.

I even had a fatal crash one moment ingame and it rebooted. Does that say something about. The R-Jtag install?
 

AllyNerd

VIP Member
Feb 25, 2013
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Philadelphia
You should be able to load your glitch image in j runner and change the power mode from there. If not your way def works.
 

xzanox

VIP Member
Nov 1, 2011
905
48
Netherlands, 1336
You may also want to try to edit your smc_config, specifically the power mode as seen in this thread here:

http://team-xecuter.com/forums/show...eezing-problem?p=930629&viewfull=1#post930629
Exactly rdubbs007, that was my next step. Just so that I don't f**k my values of something, want to be sure if I do it in this order:

1) load original nanddump in source,
2) use SMC config editor to change power mode value and save (will be nanddumpedited.bin)
3) use nanddumpedited.bin in source
4) create new image for R-Jtag
5) write image to NAND.

Correct?

After this, I have to install fsd again right?
 

Dark_Riku

VIP Member
Mar 2, 2012
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0
Exactly rdubbs007, that was my next step. Just so that I don't f**k my values of something, want to be sure if I do it in this order:

1) load original nanddump in source,
2) use SMC config editor to change power mode value and save (will be nanddumpedited.bin)
3) use nanddumpedited.bin in source
4) create new image for R-Jtag
5) write image to NAND.

Correct?

After this, I have to install fsd again right?
Just load your current NAND into the SMC editor, when it prompts you to save the nand, save to where you want and then load it in the source box and simply write image to NAND. Creating will create a new image.

Freestyle will already be configured on your HDD. All you need to do is re-install Dashlaunch, and then set your paths and you'll be good to go.
 
Last edited:
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xzanox

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Nov 1, 2011
905
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Netherlands, 1336
When you load your RJTAG nand in source, go to file> edit smc> change the value> save (it will save it as updflashedited) and then put that file into the source and flash it.
Ok, I've just done that. Changed it and saved it, indeed it saved as updflashedited.bin. I then made sure I put this new file in source and wrote to NAND.

Only now it doesn't glitch on the same settings. And when I try rater to see what's going on, it says wrong version...I have all cables connected well.

The dbg light does blink green but nada.

My original NAND just flashed back, works good boots normal.

Do i need to change my dips now I've changed my SMC?


Edit: I've wrote back my first original hacked image (updflash.bin with original values) now rater works again, but with my dip that I scored a 9.20 now isn't booting at all...wtf. I'll try different dips then. Just wanted to see if writing this updflash.bin back would make it work again or not...
 
Last edited:

xzanox

VIP Member
Nov 1, 2011
905
48
Netherlands, 1336
I wrote a new updflashedited.bin with power mode value 8080 to the NAND, doesn't boot at any of the dips. Does blink though green light. Rater goes past 15 on each dip, so then I turn it off.

Now trying 8280, it's writing at the moment, I'll report back...
Code:
Version: 10
Power Up
Waiting for POST to change
Post 20 - CB entry point reached 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post D0 - CB_A entry point reached 
Post D1 - READ_FUSES 
Post D2 - VERIFY_OFFSET_CB_B 
Post D3 - FETCH_HEADER_CB_B 
Post D5 - FETCH_CONTENTS_CB_B 
Post D6 - HMACSHA_COMPUTE_CB_B 
Post D7 - RC4_INITIALIZE_CB_B 
Post D8 - RC4_DECRYPT_CB_B 
Post D9 - SHA_COMPUTE_CB_B 
Post DA - SHA_VERIFY_CB_B 
Post F2 - Panic - SHA_VERIFY_CB_B 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post D0 - CB_A entry point reached 
Post D1 - READ_FUSES 
Post D2 - VERIFY_OFFSET_CB_B 
Post D3 - FETCH_HEADER_CB_B 
Post D4 - VERIFY_HEADER_CB_B 
Post D5 - FETCH_CONTENTS_CB_B 
Post D6 - HMACSHA_COMPUTE_CB_B 
Post D7 - RC4_INITIALIZE_CB_B 
Post D8 - RC4_DECRYPT_CB_B 
Post D9 - SHA_COMPUTE_CB_B 
Post DA - SHA_VERIFY_CB_B 
Post F2 - Panic - SHA_VERIFY_CB_B 
Shutdown
This is with 8180 with dip 6 on, anyone sees something odd about my rater or is that ok?

Sh*t men, I now can't even get it to glitch one time into dash. I think I've tried every power mode value there is. Even changed Ana fuse etc to 01, but nothing works. What is my next step? I don't think I have to go by my soldering again right? Since it was booting nicely every first or second glitch, I haven't touched nothing of those points, so... I only changed the SMC settings and now it doesn't boot :(


Edit; ok here last info and then I'm off to bed. I used another updflash.bin that I had saved on a different location and wrote that back to the NAND. Now it is booting again first or second glitch :) at least thats something right?

Ill try other stuff tomorrow again.
 
Last edited:

xzanox

VIP Member
Nov 1, 2011
905
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Netherlands, 1336
Rater does look wrong, was it set to Phat when you ran it(Default on slim- not sure if that makes a difference or what?)
Yes I did put it on phat actually. Just used the other untouched updflash and edited the SMC (8080) on it. Flashed that to my NAND. Now I had in 5 cycles a 100% ratio so all 1 boot on dip 6.

Its 2.30 am now I really am going to sleep and try tomorrow to see if it still freezes with this changed SMC config.

Thanks all for you help already, also alynerd for the pm.

Post back tomorrow
 

xzanox

VIP Member
Nov 1, 2011
905
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Netherlands, 1336
{{{FIXED}}}

Code:
Version: 10
Power Up
Waiting for POST to change
Post 7F 
Post 77 - INIT_OTHER_DRIVERS 
Post 76 - INIT_SYSTEM_ROOT 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 62 - INIT_PROCESS_OBJECTS 
Post 60 - INIT_KERNEL 
Post 20 - CB entry point reached 
Post 24 - VERIFY_OFFSET_3BL_CC 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 24 - VERIFY_OFFSET_3BL_CC 
Post 04 
Post 9F - Panic - VERIFY_SECOTP_5 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 15 - FETCH_OFFSET 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 03 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Most Fails(cumulative): 0xA0
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 7F 
Post 7E 
Post 62 - INIT_PROCESS_OBJECTS 
Post 60 - INIT_KERNEL 
Post 20 - CB entry point reached 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 24 - VERIFY_OFFSET_3BL_CC 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 04 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 18 - FETCH_CONTENTS 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 23 - INIT_SYSRAM 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4D - DECODE_FUSES 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 52 - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 6A - INIT_HAL_PHASE_1 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6F - INIT_POWER_MODE 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 77 - INIT_OTHER_DRIVERS 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post 24 - VERIFY_OFFSET_3BL_CC 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 24 - VERIFY_OFFSET_3BL_CC 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 04 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 24 - VERIFY_OFFSET_3BL_CC 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 24 - VERIFY_OFFSET_3BL_CC 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 18 - FETCH_CONTENTS 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4D - DECODE_FUSES 
Post 51 - LOAD_UPDATE_2 
Post 52 - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5F 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 6A - INIT_HAL_PHASE_1 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 70 - INIT_VIDEO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 10 - Payload/1BL started 
Post 10 - Payload/1BL started 
Post 10 - Payload/1BL started 
Post 10 - Payload/1BL started 
Post 10 - Payload/1BL started 
Post 10 - Payload/1BL started 
Post 10 - Payload/1BL started 
Post 10 - Payload/1BL started 
Post 10 - Payload/1BL started 
Post 10 - Payload/1BL started 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 18 - FETCH_CONTENTS 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 23 - INIT_SYSRAM 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 4B - LZX_EXPAND 
Post 4D - DECODE_FUSES 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 52 - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5F 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 69 - INIT_KEY_VAULT 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6F - INIT_POWER_MODE 
Post 70 - INIT_VIDEO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post 24 - VERIFY_OFFSET_3BL_CC 
Post 04 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 41 - VERIFY_OFFSET 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 10 - Payload/1BL started 
Post 18 - FETCH_CONTENTS 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 4B - LZX_EXPAND 
Post 4D - DECODE_FUSES 
Post 51 - LOAD_UPDATE_2 
Post 52 - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 69 - INIT_KEY_VAULT 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 70 - INIT_VIDEO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post 24 - VERIFY_OFFSET_3BL_CC 
Post 04 
Post 27 - VERIFY_HEADER_3BL_CC 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 23 - INIT_SYSRAM 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 4B - LZX_EXPAND 
Post 4D - DECODE_FUSES 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 52 - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 69 - INIT_KEY_VAULT 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6F - INIT_POWER_MODE 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 75 - INIT_DUMP_SYSTEM 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Reached No. of Boots Required
Rater score 100%.JPG It is a very good product R-Jtag (as also the rest of all TX products are btw)... I am very happy (well especially my customer) with these results.
Because it already booted good, I just did a set of 5 cycles to see how it would boot now. Looking good a perfecto of 10. The number 5 above was a different dip but I've stopped that as soon as it went to 5.


It was already a pretty stable booting machine, but was dealing with the freezing part spoken about in this thread. I have changed the power mode to 8080 and i am now testing the xbox for freezing. I hope i am not jinxing anything, but the box is running now for like 30 minutes and no freeze.

I will test longer and later on the day again.

As far as i am concerned if not else comes up, this thread may be closed as FIXED or ANSWERED!

Thanks to everybody who have put their effort and time reading and answering. for people reading this thread with same problems here is what i had and what i have done:

Dip 6-7 both on.
default voltage setting (so nothing bridged)
Aud_clamp and 470 (middle of the 3 switch)
Used underside cpu_rst point with blue wire (cut from slim set 55cm cut to 30 cm)
power mode was 8480, now 8080, ana fuse 02 (haven't changed this, neither the power vs control is still) 8555

SO WHAT BASICALLY HELPED THIS XBOX FROM FREEZING, WAS CHANGING THE POWER MODE FROM
8480 TO 8080 AND I GUESS USING A DIFFERENT LENGHT OF BLUE WIRE (READ ABOVE)
 
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