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guilo

Noob Account
Oct 29, 2013
5
0
Console Type: (Jasper)
NAND size: /256
Dashboard version: 2.0.16203
CB version: 6754
Screenshot of NAND details from J-Runner:
jr.jpg

J-Runner log:
POST output from J-Runner (either POST_OUT monitor or RATER output):
Code: 
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post EA 
Post 0A 
Post 6A - INIT_HAL_PHASE_1 
Post 0A 
Post EA 
Post 0A 
Post 6A - INIT_HAL_PHASE_1 
Post 0A 
Post EA 
Post 0A 
Post 6A - INIT_HAL_PHASE_1 
Post 0A 
Post 6A - INIT_HAL_PHASE_1 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post FA 
Post 0B 
Post 1B - RC4_DECRYPT 
Post 0B 
Post 0C 
Post 0D 
Post 1D - SIG_VERIFY 
Post 0D 
Post 1D - SIG_VERIFY 
Post 0D 
Post 1D - SIG_VERIFY 
Post 0D 
Post 1D - SIG_VERIFY 
Post 0D 
Post 1D - SIG_VERIFY 
Post 0D 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 1E - BRANCH 
Post 0E 
Post 66 - INIT_OBJECT_SYSTEM 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
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Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 6A - INIT_HAL_PHASE_1 
Post 7A 
Post 20 - CB entry point reached 
Shutdown
updflash.bin log (if applicable):
Image of R-JTAG board:

Images of close-up soldering to motherboard:
p1.jpgp3.jpgp2.jpgp4.jpg


Description of problem: Got 4 nand dumps. I guest next thing to do is create xell reloaded and write the file, I have checked Jtag and r-jtag. It write Ok but the console wont bootup. Reflash the original and It boot to msdash no problem. so were the problem can't pull the cpukeys

Was the console working before you started: Yes.

 
Last edited:
xzanox

xzanox

VIP Member
Nov 1, 2011
905
48
Netherlands, 1336
According to jrunner, you haven't wrote xell.

Edit: looking at your other pics, you haven't bridged 1-3 jumper on your jtag qsb.
And your soldering in general isn't to good neither, check those points on the post qsb.
 
Last edited:
chase

chase

VIP Member
Apr 11, 2004
1,073
28
Toronto, Canada
all soldering is poor ..

judging by the flux residue, i'm guessing you soldered the stby_clk point on the phat nand qsb.. there is no need to solder that.. there is a r-jtag qsb modification thread in the stickies .. just make sure you haven't done any damage there

your jtag qsb switch is in the off position..

since you're using aud_clamp, you haven't bridged the 1-3 jumper like xzanox mentioned

you don't have full j-runner log .. if that is all, then you haven't flashed xell again as xzanox mentioned :)

you don't have pic of r-jtag board

please update your post
 
Last edited:
G

guilo

Noob Account
Oct 29, 2013
5
0
after some -re-soldering
Got 3 red flash after xell reloaded.

Code: 
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post FB 
Post CF 
Post CF 
Post DF 
Post EF 
Post CF 
Post EF 
Post EF 
Post EF 
Post DF 
Post CF 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Post 70 - INIT_VIDEO_DRIVER 
Post 71 - INIT_AUDIO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 75 - INIT_DUMP_SYSTEM 
Post 77 - INIT_OTHER_DRIVERS 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post FB 
Post DF 
Post CF 
Post CF 
Post CF 
Post DF 
Post CF 
Post CF 
Post CF 
Post EF 
Post CF 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Post 70 - INIT_VIDEO_DRIVER 
Post 71 - INIT_AUDIO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 75 - INIT_DUMP_SYSTEM 
Post 77 - INIT_OTHER_DRIVERS 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post FB 
Post 7B 
Post FB 
Post EF 
Post CF 
Post CF 
Post CF 
Post EF 
Post CF 
Post EF 
Post CF 
Post DF 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Post 70 - INIT_VIDEO_DRIVER 
Post 71 - INIT_AUDIO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 75 - INIT_DUMP_SYSTEM 
Post 77 - INIT_OTHER_DRIVERS 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post FB 
Post CF 
Post CF 
Post CF 
Post CF 
Post CF 
Post CF 
Post CF 
Post CF 
Post 8F - Panic - MAINTENANCE 
Post CF 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Post 70 - INIT_VIDEO_DRIVER 
Post 71 - INIT_AUDIO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 75 - INIT_DUMP_SYSTEM 
Post 76 - INIT_SYSTEM_ROOT 
Post 77 - INIT_OTHER_DRIVERS 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post BB 
Post FB 
Post CF 
Post CF 
Post 8F - Panic - MAINTENANCE 
Post DF 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Post 70 - INIT_VIDEO_DRIVER 
Post 71 - INIT_AUDIO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 75 - INIT_DUMP_SYSTEM 
Post 76 - INIT_SYSTEM_ROOT 
Post 77 - INIT_OTHER_DRIVERS 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post DB - BRANCH_CB_B 
Post FB 
Post CF 
Post DF 
Post EF 
Post CF 
Post CF 
Post CF 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Post 70 - INIT_VIDEO_DRIVER 
Post 71 - INIT_AUDIO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 75 - INIT_DUMP_SYSTEM 
Post 76 - INIT_SYSTEM_ROOT 
Post 77 - INIT_OTHER_DRIVERS 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Post 70 - INIT_VIDEO_DRIVER 
Post 71 - INIT_AUDIO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 75 - INIT_DUMP_SYSTEM 
Post 76 - INIT_SYSTEM_ROOT 
Post 77 - INIT_OTHER_DRIVERS 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Post 70 - INIT_VIDEO_DRIVER 
Post 71 - INIT_AUDIO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 75 - INIT_DUMP_SYSTEM 
Post 76 - INIT_SYSTEM_ROOT 
Post 77 - INIT_OTHER_DRIVERS 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Post 70 - INIT_VIDEO_DRIVER 
Post 71 - INIT_AUDIO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 75 - INIT_DUMP_SYSTEM 
Post 77 - INIT_OTHER_DRIVERS 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Post 70 - INIT_VIDEO_DRIVER 
Post 71 - INIT_AUDIO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 75 - INIT_DUMP_SYSTEM 
Post 76 - INIT_SYSTEM_ROOT 
Post 77 - INIT_OTHER_DRIVERS 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Post F9 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Post 70 - INIT_VIDEO_DRIVER 
Post 71 - INIT_AUDIO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 75 - INIT_DUMP_SYSTEM 
Post 76 - INIT_SYSTEM_ROOT 
Post 77 - INIT_OTHER_DRIVERS 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
Power Up
Waiting for POST to change
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 7B 
Post FB 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 5B - INIT_KEYRING 
Post 5C - INIT_KEYS 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 5F 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6E - INIT_SETTINGS 
Post 6F - INIT_POWER_MODE 
Post 70 - INIT_VIDEO_DRIVER 
Post 71 - INIT_AUDIO_DRIVER 
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init 
Post 73 - INIT_SATA_DRIVER 
Post 75 - INIT_DUMP_SYSTEM 
Post 77 - INIT_OTHER_DRIVERS 
Post 78 - INIT_STFS_DRIVER 
Post 79 - LOAD_XAM 
Shutdown
 
Last edited:
chase

chase

VIP Member
Apr 11, 2004
1,073
28
Toronto, Canada
first, your post output is all wrong... can you update with new pictures - especially a clear and detailed shot of post qsb pls..

there are 6 dips, 3 voltage settings and 3 resistance settings to go through.. have you tried them all ?

its normal to get RROD while tuning until you reach optimal setting
 
Last edited:
G

guilo

Noob Account
Oct 29, 2013
5
0
Ok after some gliching I got this:
Initializing nanddump1.bin..
CpuKey is Correct
Added Key to Database
Extracting..
Saving SMC_en.bin
Saving SMC_dec.bin
Saving KV_en.bin
Saving KV_dec.bin
Saving smc_config.bin
Finished
Jasper BB
Nand Initialization Finished
Moving All files from output folder to C:\Users\Guilo\Desktop\J-Runner\020551190907
Options.ini file was altered successfully
Use Edited Options Selected
Using edited settings
Load Files Initiliazation Finished
Clean SMC detected
Patching Jasper version 2.3 SMC at offset 0x12BA
16203
Started Creation of the 16203 xebuild image
KV Info saved to file
---------------------------------------------------------------
xeBuild v1.09.639
---------------------------------------------------------------
base path changed to C:\Users\Guilo\Desktop\J-Runner\xeBuild
---- { Image Build Mode } ----
building jtag image




******* WARNING: could not patch SMC reset limit!


---------------------------------------------------------------
C:\Users\Guilo\Desktop\J-Runner\020551190907\updflash.bin image built, info:
---------------------------------------------------------------
Kernel : 2.0.16203.0
Console : Jasper (big block)
NAND size : 64MiB (system only)
Build : JTAG
Xell : power on console with IR power button
Serial : 020551190907
ConsoleId : 006070955495
MoboSerial: 8920934202479097
Mfg Date : 02/23/2009
CPU Key : xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
1BL Key : xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
DVD Key : xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
CF LDV : 9
KV type : type2 (hashed - unchecked, master key not available)
---------------------------------------------------------------
xeBuild Finished. Have a nice day.
---------------------------------------------------------------
Use Edited Options de-Selected
Saved to C:\Users\Guilo\Desktop\J-Runner\020551190907
Image is Ready
Jasper 256MB Manually Selected
Version: 10

thanks to all you.
now its time to move on.
 
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