R-JTAG Cannot boot to Xell Reloaded

B

banjojohn

Junior Member
Oct 15, 2011
17
0
Console Type: Jasper
NAND size: 16 MB
Dashboard version: 2.0.15574
CB version: Will get back on that once I get home, sorry
Screenshot of NAND details from J-Runner:
Forgot that one before I went to work, will do if it's relevant
J-Runner log:

I haven't got other logs than this, as I accidently cleared the log. I could find one those 'good' combinations mentioned below again and post it, once I get home from work.

Code: 
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post 8A - Panic - DECREMENTER 
Post 82 - Panic - DATA_STORAGE 
Post A2 - Panic - VERIFY_SECOTP_8 
Post 82 - Panic - DATA_STORAGE 
Post A2 - Panic - VERIFY_SECOTP_8 
Post 82 - Panic - DATA_STORAGE 
Post A2 - Panic - VERIFY_SECOTP_8 
Post 82 - Panic - DATA_STORAGE 
Post A2 - Panic - VERIFY_SECOTP_8 
Post 82 - Panic - DATA_STORAGE 
Post A2 - Panic - VERIFY_SECOTP_8 
Post 82 - Panic - DATA_STORAGE 
Post A2 - Panic - VERIFY_SECOTP_8 
Post 82 - Panic - DATA_STORAGE 
Post A2 - Panic - VERIFY_SECOTP_8 
Post 82 - Panic - DATA_STORAGE 
Post A2 - Panic - VERIFY_SECOTP_8 
Post 82 - Panic - DATA_STORAGE 
Post A2 - Panic - VERIFY_SECOTP_8 
Post 82 - Panic - DATA_STORAGE 
Post A2 - Panic - VERIFY_SECOTP_8 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post E0 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 95 - Panic - VERIFY_HEADER 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 95 - Panic - VERIFY_HEADER 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post E0 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 95 - Panic - VERIFY_HEADER 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Most Fails(cumulative): 0xA0
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post E0 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post E0 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 95 - Panic - VERIFY_HEADER 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post E0 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post E0 
Post 80 
Post E0 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 95 - Panic - VERIFY_HEADER 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic -ic) 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E0 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post E0 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 95 - Panic - VERIFY_HEADER 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Most Fails(cumulative): 0xA0
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post FE 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 95 - Panic - VERIFY_HEADER 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post E0 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post E0 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post E0 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 91 - Panic - THERMAL_MANAGEMENT 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 95 - Panic - VERIFY_HEADER 
Post 98 - Panic - NEXT_STAGE_SIZE 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post E0 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 95 - Panic - VERIFY_HEADER 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Most Fails(cumulative): 0xA0
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post FE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post CE 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 95 - Panic - VERIFY_HEADER 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Most Fails(cumulative): 0xA0
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 95 - Panic - VERIFY_HEADER 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post 91 - Panic - THERMAL_MANAGEMENT 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 9B - Panic - VERIFY_SECOTP_1 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 9D - Panic - VERIFY_SECOTP_3 
Post 9E - Panic - Panic - VERIFY_SECOTP_4 
Post A0 - Panic - VERIFY_SECOTP_6 
Post A1 - Panic - VERIFY_SECOTP_7 
Post A0 - Panic - VERIFY_SECOTP_6 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post FE 
Post 9F - Panic - VERIFY_SECOTP_5 
Post B4 - Panic - LZX_EXPAND 
Post BD 
Post FD 
Post 83 - Panic - DATA_SEGMENT 
Post 83 - Panic - DATA_SEGMENT 
Post 8F - Panic - MAINTENANCE 
Post FA 
Post A7 - Panic - VERIFY_HEADER_3BL_CC 
Post 8F - Panic - MAINTENANCE 
Post D7 - RC4_INITIALIZE_CB_B 
Post 8F - Panic - MAINTENANCE 
Post 8F - Panic - MAINTENANCE 
Post FB 
Post 80 
Most Fails(cumulative): 0xA0
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 0E 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 0E 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 0E 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 0E 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 0E 
Post 0A 
Post 08 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 08 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 08 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 08 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 08 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 08 
Post 7C 
Post 61 - INIT_HAL_PHASE_0 
Post 60 - INIT_KERNEL 
Post 01 
Post 78 - INIT_STFS_DRIVER 
Post 43 - VERIFY_HEADER 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 10 - Payload/1BL started 
Post 60 - INIT_KERNEL 
Post 09 
Post 60 - INIT_KERNEL 
Post 08 
Post 40 - Entrypoint of CD reached 
Post 48 - SHA_COMPUTE 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 43 - VERIFY_HEADER 
Post 60 - INIT_KERNEL 
Post 7F 
Post 0F 
Post 03 
Post 78 - INIT_STFS_DRIVER 
Post 60 - INIT_KERNEL 
Post 3F 
Post 60 - INIT_KERNEL 
Post 60 - INIT_KERNEL 
Post 01 
Post 60 - INIT_KERNEL 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 3F 
Post 60 - INIT_KERNEL 
Post 44 - FETCH_CONTENTS 
Post 10 - Payload/1BL started 
Post 18 - FETCH_CONTENTS 
Post 20 - CB entry point reached 
Post 06 
Post 20 - CB entry point reached 
Post 24 - VERIFY_OFFSET_3BL_CC 
Post 03 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 40 - Entrypoint of CD reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 40 - Entrypoint of CD reached 
Post 06 
Post 20 - CB entry point reached 
Post 01 
Post 01 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 60 - INIT_KERNEL 
Post 04 
Post 60 - INIT_KERNEL 
Post 47 - RC4_DECRYPT 
Post 01 
Post 73 - INIT_SATA_DRIVER 
Post 60 - INIT_KERNEL 
Post 08 
Post 1F 
Post 1F 
Post 01 
Post 43 - VERIFY_HEADER 
Post 30 - VERIFY_OFFSET_4BL_CD 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 80 
Post 80 
Post 80 
Post 80 
Post 80 
Post 80 
Post 80 
Post 80 
Post 80 
Post 80 
Post 82 - Panic - DATA_STORAGE 
Post 80 
Post C7 - LZX_EXPAND_7 
Post 80 
Post E0 
Post 80 
Post C0 
Post 80 
Post E0 
Post 80 
Post E0 
Post 80 
Post C7 - LZX_EXPAND_7 
Post 80 
Post E0 
Post 80 
Post 9F - Panic - VERIFY_SECOTP_5 
Post 80 
Post E0 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post E0 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post C0 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post 84 - Panic - INSTRUCTION_STORAGE 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Most Fails(cumulative): 0xA0
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 80 
Post 80 
Post 80 
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post 80 
Post 8D - Panic - TRACE 
Post 80 
Post E0 
Post 80 
Post 90 - Panic - VMX_ASSIST 
Post 80 
Post E0 
Post 80 
Post 98 - Panic - NEXT_STAGE_SIZE 
Post 80 
Post E0 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post E0 
Post 80 
Post 86 - Panic - EXTERNAL 
Post 80 
Post E0 
Post 80 
Post F8 
Post 80 
Post E0 
Post 80 
Post A1 - Panic - VERIFY_SECOTP_7 
Post 80 
Post 8D - Panic - TRACE 
Post 80 
Post 8D - Panic - TRACE 
Post 80 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 80 
Post E0 
Post 80 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 80 
Post E0 
Post 80 
Post C0 
Post 80 
Post E0 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post 81 - Panic - MACHINE_CHECK 
Post 80 
Post C7 - LZX_EXPAND_7 
Post 80 
Post E0 
Post 80 
Post E0 
Post 80 
Post E0 
Post 80 
Post E0 
Post 80 
Post E0 
Post 80 
Post BC 
Post 80 
Post F1 - Panic - VERIFY_HEADER_CB_B 
Post 80 
Post A1 - Panic - VERIFY_SECOTP_7 
Post 80 
Post E3 
Post 80 
Post 89 - Panic - FPU_UNAVAILABLE 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post 80 
Post E0 
Post 80 
Most Fails(cumulative): 0xA0
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post FE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post FE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post CE 
Post 80 
Post E0 
Post 80 
Post E0 
Post 80 
Post 90 - Panic - VMX_ASSIST 
Post 80 
Post E0 
Post 80 
Post E0 
Post 80 
Post 83 - Panic - DATA_SEGMENT 
Post 80 
Post E0 
Post 80 
Post 8D - Panic - TRACE 
Post 80 
Post E1 
Post 80 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post FE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post FE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post FE 
Post 80 
Post E0 
Post 80 
Post E0 
Post 80 
Post 86 - Panic - EXTERNAL 
Post 80 
Post B4 - Panic - LZX_EXPAND 
Post 80 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post FE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post FE 
Post 80 
Post 83 - Panic - DATA_SEGMENT 
Post 80 
Post E8 
Post 80 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post EE 
Post 8E - Panic - VPU_UNAVAILABLE 
Post 80 
Post E0 
Post 80 
Post FC 
Post 80 
Post E8 
Post 80 
Post E0 
Post 80 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 80 
Post E0 
Post 80 
Post 8C - Panic - SYSTEM_CALL 
Post 80 
Post E0 
Post 80 
Post 84 - Panic - INSTRUCTION_STORAGE 
Post 80 
Post E0 
Post 80 
Post E1 
Post 80 
Post C7 - LZX_EXPAND_7 
Post 80 
Post 8C - Panic - SYSTEM_CALL 
Post 80 
Post 9A 
Post 80 
Post E0 
Post 80 
Post 8C - Panic - SYSTEM_CALL 
Post 80 
Post E0 
Post 80 
Post 86 - Panic - EXTERNAL 
Post 80 
Post 8C - Panic - SYSTEM_CALL 
Post 80 
Post 83 - Panic - DATA_SEGMENT 
Post 80 
Post E1 
Post 80 
Post C4 - LZX_EXPAND_4 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post 80 
Post 8C - Panic - SYSTEM_CALL 
Post 80 
Post 82 - Panic - DATA_STORAGE 
Post 80 
Shutdown
Version: 00
Wrong Version.
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post 86 - Panic - EXTERNAL 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post E6 
Post 86 - Panic - EXTERNAL 
Post E6 
Post A6 - Panic - LOCATE_3BL_CC 
Post 86 - Panic - EXTERNAL 
Post E6 
Post 86 - Panic - EXTERNAL 
Post C6 - LZX_EXPAND_6 
Post E6 
Post 86 - Panic - EXTERNAL 
Post E6 
Post 86 - Panic - EXTERNAL 
Post E6 
Post 86 - Panic - EXTERNAL 
Post E6 
Post 86 - Panic - EXTERNAL 
Post 80 
Post E3 
Post 80 
Post 91 - Panic - THERMAL_MANAGEMENT 
Post 80 
Post E0 
Post 80 
Post 98 - Panic - NEXT_STAGE_SIZE 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post BE 
Post 80 
Post E0 
Post 80 
Post E0 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post 81 - Panic - MACHINE_CHECK 
Post 80 
Post E3 
Post 80 
Post C0 
Post 80 
Post 88 - Panic - PROGRAM 
Post 80 
Post E0 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post 8D - Panic - TRACE 
Post 80 
Post C1 - LZX_EXPAND_1 
Post 80 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 80 
Post BE 
Post 80 
Post 91 - Panic - THERMAL_MANAGEMENT 
Post 80 
Post C0 
Post 80 
Post E0 
Post 80 
Post 86 - Panic - EXTERNAL 
Post 80 
Post 9C - Panic - VERIFY_SECOTP_2 
Post 80 
Post E0 
Post 80 
Post 90 - Panic - VMX_ASSIST 
Post 80 
Post 86 - Panic - EXTERNAL 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post E0 
Post 80 
Most Fails(cumulative): 0xA0
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 40 - Entrypoint of CD reached 
Post 40 - Entrypoint of CD reached 
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post AE - Panic - UNEXPECTED_INTERRUPT 
Post 8E - Panic - VPU_UNAVAILABLE 
Post E6 
Post 86 - Panic - EXTERNAL 
Post E6 
Post 86 - Panic - EXTERNAL 
Post E6 
Post 86 - Panic - EXTERNAL 
Post E6 
Post 86 - Panic - EXTERNAL 
Post E6 
Post 86 - Panic - EXTERNAL 
Post E6 
Post 86 - Panic - EXTERNAL 
Post E6 
Post 86 - Panic - EXTERNAL 
Post E6 
Post 86 - Panic - EXTERNAL 
Post F6 
Post 80 
Post C0 
Post 80 
Post A4 - Panic - VERIFY_SECOTP_10 
Post 80 
Post C0 
Post 80 
Post 88 - Panic - PROGRAM 
Post 80 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post 8A - Panic - DECREMENTER 
Post AA - Panic - VERIFY_OFFSET_4BL_CD 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post AA - Panic - VERIFY_OFFSET_4BL_CD 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post 80 
Post E3 
Post 80 
Post BC 
Post 80 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post 8A - Panic - DECREMENTER 
Post AA - Panic - VERIFY_OFFSET_4BL_CD 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post FA 
Post 8A - Panic - DECREMENTER 
Post 9A 
Post 8A - Panic - DECREMENTER 
Post FA 
Post 8A - Panic - DECREMENTER 
Post FA 
Post 8A - Panic - DECREMENTER 
Post FA 
Post 8A - Panic - DECREMENTER 
Post FA 
Post 8A - Panic - DECREMENTER 
Post FA 
Post 8A - Panic - DECREMENTER 
Post FA 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post E0 
Post 80 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 04 
Post 04 
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post 8A - Panic - DECREMENTER 
Post AA - Panic - VERIFY_OFFSET_4BL_CD 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post AA - Panic - VERIFY_OFFSET_4BL_CD 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post EA 
Post 8A - Panic - DECREMENTER 
Post 80 
Post E0 
Post 80 
Post E0 
Post 80 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post 8A - Panic - DECREMENTER 
Post 80 
Post B4 - Panic - LZX_EXPAND 
Post 80 
Post E8 
Post 80 
Post 8C - Panic - SYSTEM_CALL 
Post 80 
Post E8 
Post 80 
Post E0 
Post 80 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 80 
Post E0 
Post 80 
Post F1 - Panic - VERIFY_HEADER_CB_B 
Post 80 
Post E3 
Post 80 
Post 8F - Panic - MAINTENANCE 
Post 80 
Post 8C - Panic - SYSTEM_CALL 
Post 80 
Post E0 
Post 80 
Post 98 - Panic - NEXT_STAGE_SIZE 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post 8A - Panic - DECREMENTER 
Post AA - Panic - VERIFY_OFFSET_4BL_CD 
Post 8A - Panic - DECREMENTER 
Post 82 - Panic - DATA_STORAGE 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post E1 
Post 80 
Post E0 
Post 80 
Post 92 - Panic - 1BL is executed on wrong CPU thread (panic) 
Post 80 
Post F1 - Panic - VERIFY_HEADER_CB_B 
Post 80 
Post C0 
Post 80 
Post C1 - LZX_EXPAND_1 
Post 80 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post 8A - Panic - DECREMENTER 
Post D8 - RC4_DECRYPT_CB_B 
Post 80 
Post 88 - Panic - PROGRAM 
Post 80 
Post 86 - Panic - EXTERNAL 
Post 80 
Post E0 
Post 80 
Post E0 
Post 80 
Post C7 - LZX_EXPAND_7 
Post 80 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post 8A - Panic - DECREMENTER 
Post AA - Panic - VERIFY_OFFSET_4BL_CD 
Post 8A - Panic - DECREMENTER 
Post D6 - HMACSHA_COMPUTE_CB_B 
Post 80 
Post C0 
Post 80 
Post C0 
Post 80 
Post 86 - Panic - EXTERNAL 
Post 80 
Post E3 
Post 80 
Post 81 - Panic - MACHINE_CHECK 
Post 80 
Post 81 - Panic - MACHINE_CHECK 
Post 80 
Post 8F - Panic - MAINTENANCE 
Post 80 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post 8A - Panic - DECREMENTER 
Post 82 - Panic - DATA_STORAGE 
Post BF 
Post 80 
Post A1 - Panic - VERIFY_SECOTP_7 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post E0 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post E0 
Post 80 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post C0 
Post 80 
Post 8F - Panic - MAINTENANCE 
Post 80 
Most Fails(cumulative): 0xA0
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 80 
Post 8E - Panic - VPU_UNAVAILABLE 
Post 8A - Panic - DECREMENTER 
Post 80 
Post 98 - Panic - NEXT_STAGE_SIZE 
Post 80 
Post E3 
Post 80 
Shutdown
Description of problem:

I'm using the R-JTAG Ultimate kit and have done a AUD_cLAMP install (cpu_rst on backside of MB).

I'm not able to boot into Xell Reloaded. I have successfully retrieved the NAND, created and written Xell Reloaded, but I cannot get it to boot into Xell. I have plugged TV/Monitor to both HDMI and the other port but no picture. I have also tried looking in my routers connected hosts, while having the Xbox have a network cable plugged in (not found).

I've tried with no voltage bridge on the R-JTAG, having DIPs 7 and 8 ON + 1-6, one at a time and likewise while bridging for 1.2v and 1.8v. I have also fiddled with the R-JTAG QSB at 330 and 470. 95% of the time there's just a whole bunch of panics, but I guess that's just entirely normal. I have gotten better results on a few different settings, among others DIPs 3,7 and 8, 1.2v and 470 but it never got to having video output.

I'm not a master solder (far from) but I've gone over them all and they whould all be ok IMHO.

What I'd like are some tips on what I could look into. I have been getting perhaps a handful of combinations ending in most POST 0x21. In the guide it says that means something went wrong, possible glitch timing and that 0x21 and usually just one DIP from the optimal. Right now I'm not going for optimal of course. I just want to retrieve the key. But when I find one of those 0x21 it never works shifting the DIP one place.

I have tried writing the original NAND back to the Xbox and it booted just fine, when turning the JTAG QSB off. So I haven't destroyed the box (yet).

Any help is greatly appreciated!!

Was the console working before you started: Yes
 

Attachments

Last edited:
D

daman10

VIP Member
Jun 27, 2012
594
33
Re: R-JTAG Cannot to Xell Reloaded

Dunno if it makes a difference but you hav missed 3 points on the post QSB
 
RF1911

RF1911

VIP Member
Feb 2, 2011
157
0
Re: R-JTAG Cannot to Xell Reloaded

Post 9E = 10011110 (this is what u have and it's wrong)
Post 1E = 00011110

Check soldering on postbit 7, the one with that huge solder blob.
 
B

banjojohn

Junior Member
Oct 15, 2011
17
0
Re: R-JTAG Cannot to Xell Reloaded

daman10 said:
Dunno if it makes a difference but you hav missed 3 points on the post QSB
Click to expand...
You might be totally correct, but how can you possible see that on that pic? :D

RF1911 said:
Post 9E = 10011110 (this is what u have and it's wrong)
Post 1E = 00011110

Check soldering on postbit 7, the one with that huge solder blob.
Click to expand...
I will go over all those points again. Could you perhaps enlighten me and tell how you know that single bit is connected to that exact point (I'm just curious)...


By the way, thanks for some speedy feedback. That's amazing!!
 
E

[email protected]

VIP Member
Jun 21, 2012
383
0
Re: R-JTAG Cannot to Xell Reloaded

I suspect that green debug LED is not blinking. If it isn't it doesn't make any sense to switch DIPs or solder voltage jumper. POST log is terrible.
 
B

banjojohn

Junior Member
Oct 15, 2011
17
0
Re: R-JTAG Cannot to Xell Reloaded

[email protected] said:
I suspect that green debug LED is not blinking. If it isn't it doesn't make any sense to switch DIPs or solder voltage jumper. POST log is terrible.
Click to expand...
Green is blinking on R-JTAG. Most of the post log is from when I had bridged 1.8v (as it was when taking the picture). I have had some better POSTs of course. I will provide a better log once I get home, check the soldering on the post and try again!
 
xzanox

xzanox

VIP Member
Nov 1, 2011
905
48
Netherlands, 1336
If you check the soldering, flux it and retouch all the points so that you are sure you all points are connected well. Remove excessive tin where necessary. I had the same problem booting in xell with a falcon R-Jtag, solved it by redoing the post points (and i also redid the qsb points just to be sure)
 
B

banjojohn

Junior Member
Oct 15, 2011
17
0
xzanox said:
If you check the soldering, flux it and retouch all the points so that you are sure you all points are connected well. Remove excessive tin where necessary. I had the same problem booting in xell with a falcon R-Jtag, solved it by redoing the post points (and i also redid the qsb points just to be sure)
Click to expand...
Sounds good. Thanks all. I will return with result/progress.
Go ahead and post if there's anything else to add...
 
RF1911

RF1911

VIP Member
Feb 2, 2011
157
0
Re: R-JTAG Cannot to Xell Reloaded

banjojohn said:
You might be totally correct, but how can you possible see that on that pic? :D



I will go over all those points again. Could you perhaps enlighten me and tell how you know that single bit is connected to that exact point (I'm just curious)...


By the way, thanks for some speedy feedback. That's amazing!!
Click to expand...
I dont look at soldering, i look at post log. Ive made sure that the RJTAG guide shows what expected good post log is. So if you get 9X instead of 1X, where x is 0 to E, it means that most significant bit is always read as '1', thus your postbit 1 is floating, thus not soldered, thus always read as '1' by the chip.
 
Last edited:
B

banjojohn

Junior Member
Oct 15, 2011
17
0
So I have resoldered on the POST QSB and removed the 1.8 bridge, and retried with recommended Jasper settings (470, DIPs 5, 7 and 8). This is the output ( some with DIP 5, some with 4):

Code: 
Version: 10
Power Up
Waiting for POST to change
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 01 
Post E0 
Post E0 
Post 20 - CB entry point reachted 
Post C0 
Post 03 
Post 01 
Post 03 
Post E0 
Post E0 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
ETCH_CONTENTS 
Post 3C 
Pos E0 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post E1 
Post 18 - FETCH_CONTENTS 
Post 18 - FETCH_CONTENTS 
Post E0 
Post 84 - Panic - INSTRUCTION_STORAGE 
Post E1 
Post 1A - RC4_INITIALIZE 
Post FE 
Post 80 
Post 04 
Post 44 - FETCH_CONTENTS 
Post 0C 
Post E3 
Post 38 - SIG_VERIFY_4BL_CD 
Post 91 - Panic - THERMAL_MANAGEMENT 
Post 86 - Panic - EXTERNAL 
Post 20 - CB entry point reached 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post C0 
Post 20 - CB entry point reached 
Post 7F 
Post 0C 
Post E0 
Post C2 - LZX_EXPAND_2 
Post 91 - Panic - THERMAL_MANAGEMENT 
Post 3E 
Post E0 
Post 0D 
Post 40 - Entrypoint of CD reached 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post 0E 
Post 2E - HWINIT 
Post E0 
Post E0 
Post C0 
Post 80 
Post E0 
Post 1F 
Post 60 - INIT_KERNEL 
Post 06 
Post E0 
Post 0D 
Post 82 - Panic - DATA_STORAGE 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 0C 
Post 18 - FETCH_CONTENTS 
Post 01 
Post C3 - LZX_EXPAND_3 
Post 0C 
Post E0 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 86 - Panic - EXTERNAL 
Post 61 - INIT_HAL_PHASE_0 
Post 84 - Panic - INSTRUCTION_STORAGE 
Post 03 
Post 01 
Post 80 
Post 0C 
Post 01 
Post 01 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 3E 
Post 7F 
Post E0 
Post 1E - BRANCH 
Post 48 - SHA_COMPUTE 
Post 1E - BRANCH 
Post D0 - CB_A entry point reached 
Post 91 - Panic - THERMAL_MANAGEMENT 
Post 60 - INIT_KERNEL 
Post 84 - Panic - INSTRUCTION_STORAGE 
Post 3C 
Post 10 - Payload/1BL started 
Post 3C 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post FC 
Post E0 
Post 03 
Post 07 
Post 10 - Payload/1BL started 
Post E0 
Post E0 
Post 0C 
Post 0F 
Post 01 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 40 - Entrypoint of CD reached 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 0E 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 43 - VERIFY_HEADER 
Post 1F 
Post 1E - BRANCH 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 0C 
Post 20 - CB entry point reached 
Post 50 - LOAD_UPDATE_1 
Post 40 - Entrypoint of CD reached 
Post 3E 
Post 18 - FETCH_CONTENTS 
Post 0C 
Post 7F 
Post 04 
Post 0D 
Post 40 - Entrypoint of CD reached 
Post 61 - INIT_HAL_PHASE_0 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 1F 
Post 60 - INIT_KERNEL 
Post 60 - INIT_KERNEL 
Post 0D 
Post 48 - SHA_COMPUTE 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 01 
Post 1F 
Post 60 - INIT_KERNEL 
Post 06 
Post 61 - INIT_HAL_PHASE_0 
Post 60 - INIT_KERNEL 
Post 60 - INIT_KERNEL 
Post 20 - CB entry point reached 
Post 60 - INIT_KERNEL 
Post 06 
Post 12 - FSB_CONFIG_RX_STATE 
Post 71 - INIT_AUDIO_DRIVER 
Post 03 
Post 3E 
Post 0D 
Post 10 - Payload/1BL started 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 01 
Post 06 
Post 7F 
Post 0F 
Post 60 - INIT_KERNEL 
Post 42 - FETCH_HEADER 
Post 60 - INIT_KERNEL 
Post 60 - INIT_KERNEL 
Post 60 - INIT_KERNEL 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 7F 
Post 5F 
Post 45 - HMACSHA_COMPUTE 
Post 04 
Post 40 - Entrypoint of CD reached 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 52 - BRANCH 
Post 56 
Post 5E - INIT_SOC_INT_COMPLETE 
Post 56 
Post 46 - RC4_INITIALIZE 
Post 42 - FETCH_HEADER 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 40 - Entrypoint of CD reached 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 40 - Entrypoint of CD reached 
Post 40 - Entrypoint of CD reached 
Post 40 - Entrypoint of CD reached 
Post 40 - Entrypoint of CD reached 
Post 40 - Entrypoint of CD reached 
Post C2 - LZX_EXPAND_2 
Post F6 
Post 40 - Entrypoint of CD reached 
Post F6 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 40 - Entrypoint of CD reached 
Post 40 - Entrypoint of CD reached 
Post C2 - LZX_EXPAND_2 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post DE 
Post FE 
Post DE 
Post E6 
Post 40 - Entrypoint of CD reached 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post DF 
Post FE 
Post 42 - FETCH_HEADER 
Post DF 
Post DF 
Post 40 - Entrypoint of CD reached 
Post DF 
Post 42 - FETCH_HEADER 
Shutdown
Version: 10
Power Up
Waiting for POST to change
Post 0E 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post F8 
Post E0 
Post 20 - CB entry point reached 
Post 80 
Post C3 - LZX_EXPAND_3 
Post E0 
Post 0C 
Post 03 
Post 06 
Post 1F 
Post E0 
Post C3 - LZX_EXPAND_3 
Post 18 - FETCH_CONTENTS 
Post 80 
Post 04 
Post 04 
Post FE 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 09 
Post 1E - BRANCH 
Post C0 
Post 07 
Post 3E 
Post E0 
Post 38 - SIG_VERIFY_4BL_CD 
Post 60 - INIT_KERNEL 
Post 0C 
Post F8 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 80 
Post 44 - FETCH_CONTENTS 
Post 1C - SHA_COMPUTE 
Post 18 - FETCH_CONTENTS 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post E0 
Post C4 - LZX_EXPAND_4 
Post 03 
Post 80 
Post 8F - Panic - MAINTENANCE 
Post 06 
Post E0 
Post 03 
Post 8F - Panic - MAINTENANCE 
Post 18 - FETCH_CONTENTS 
Post D0 - CB_A entry point reached 
Post E0 
Post E0 
Post F1 - Panic - VERIFY_HEADER_CB_B 
Post 7C 
Post E0 
Post E0 
Post C0 
Post 18 - FETCH_CONTENTS 
Post E0 
Post E0 
Post C0 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 60 - INIT_KERNEL 
Post 18 - FETCH_CONTENTS 
Post E0 
Post 1A - RC4_INITIALIZE 
Post E0 
Post 61 - INIT_HAL_PHASE_0 
Post E0 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post E0 
Post 0C 
Post 91 - Panic - THERMAL_MANAGEMENT 
Post 61 - INIT_HAL_PHASE_0 
Post E0 
Post 03 
Post 0F 
Post E0 
Post 48 - SHA_COMPUTE 
Post 10 - Payload/1BL started 
Post 7F 
Post 20 - CB entry point reached 
TIMEOUT or SMC CORRUPTED - Shutting Down
Shutdown
Power Up
Waiting for POST to change
Post 0E 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post 2A - RC4_INITIALIZE_3BL_CC 
Post 0A 
Post FC 
Post 18 - FETCH_CONTENTS 
Post E0 
Post 41 - VERIFY_OFFSET 
Post E0 
Post 3F 
Post 10 - Payload/1BL started 
Post E3 
Post C7 - LZX_EXPAND_7 
Post 86 - Panic - EXTERNAL 
Post 7F 
Post FC 
Post 7F 
Post 03 
Post 24 - VERIFY_OFFSET_3BL_CC 
Post 0C 
Post E0 
Post C0 
Post E0 
Post 01 
Post 80 
Post 24 - VERIFY_OFFSET_3BL_CC 
Post E0 
Post 80 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 03 
Post 80 
Post F8 
Post 8F - Panic - MAINTENANCE 
Post 0C 
Post 01 
Post 1E - BRANCH 
Post 80 
Post F8 
Post 10 - Payload/1BL started 
Post 0D 
Post 0C 
Post 86 - Panic - EXTERNAL 
Post 60 - INIT_KERNEL 
Post 78 - INIT_STFS_DRIVER 
Post D0 - CB_A entry point reached 
Post 10 - Payload/1BL started 
Post C2 - LZX_EXPAND_2 
Post E1 
Post F1 - Panic - VERIFY_HEADER_CB_B 
Post C0 
Post C2 - LZX_EXPAND_2 
Post 3C 
Post 3E 
Post 3E 
Post 3F 
Post 20 - CB entry point reached 
Post 06 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 03 
Post 20 - CB entry point reached 
Post 1C - SHA_COMPUTE 
Post 03 
Post E0 
Post 86 - Panic - EXTERNAL 
Post 0C 
Post E0 
Post E0 
Post 03 
Post 60 - INIT_KERNEL 
Post 04 
Post 20 - CB entry point reached 
Post 7F 
Post 5F 
Post 5C - INIT_KEYS 
Post 1C - SHA_COMPUTE 
Post 0C 
Post 04 
Shutdown
Still no video output though, of course. Can you guys give me another nudge in the right direction?
 
xzanox

xzanox

VIP Member
Nov 1, 2011
905
48
Netherlands, 1336
And have you tried also every other dip one at a time after you redid the solder points? Maybe you can upload a few pics of the newly touched solder points on your post out qsb. Just remember that if your points weren't good before, you have to try all the settings (dips, voltage, jumpers) again.
 
B

banjojohn

Junior Member
Oct 15, 2011
17
0
Actually the R-JTAG isn't blinking green anymore. Last I checked it was, but I don't know exactly when it stopped. So what exactly makes it blink? I assume the problem is the solderings... are there any specific to look for, I mean I guess some can be ruled out for this error?
 
E

[email protected]

VIP Member
Jun 21, 2012
383
0
banjojohn said:
Actually the R-JTAG isn't blinking green anymore. Last I checked it was, but I don't know exactly when it stopped. So what exactly makes it blink? I assume the problem is the solderings... are there any specific to look for, I mean I guess some can be ruled out for this error?
Click to expand...
in my case it didn't blink when I mixed up two bits doing wire install
 
E

[email protected]

VIP Member
Jun 21, 2012
383
0
keil423 said:
You still haven't soldered the last 3 points on the post QSBs.
When you built your glitch image did you remember to select the Aud_Clamp option in Jrunner?
Click to expand...
this won't solve his problems, those points on POST QSB are optional, and even without aud_clamp tick it should boot to E79 on the screen
 
B

banjojohn

Junior Member
Oct 15, 2011
17
0
I decided to kind of start from scratch. I reloaded the original NAND and guess what? - RROD. So I've f****d up somewhere. I guess that could be anywhere I've soldered, or? I haven't looked into the error code reported from the RROD (starts with those standard 3 lights (excluding the top right one, I think), but right now I haven't got the complete error code. Would that be useful at all at this step.
By the way, I am looking into persuading one of my friends to help. He does a much better solder job than myself.

Regarding the RROD: I removed the R-JTAG, the JRunner and turned the QSB off. Should start with original NAND to my knowlegde.
 
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