R-JTAG E79, and POST A0 PANIC

L

Lukeshepp

Noob Account
Dec 3, 2013
4
0
Hello,
First - so i dont get shouted at.. ;)

Console Type: Jasper
NAND size: 16
Dashboard version: 16537
Was the console working before you started: Ofcourse!

So, the problem. Ill try and say everything in the first post.
I have an R-JTAG ultimate kit, and have correctly read the original nand twice, they compared and succeeded, (Two bad blocks but dont really matter).
Then i created an XeLL image, Clicking - JTAG -> R-JTAG, (Have tried both with aud_clamp and without, swapping soldering too as necessary . I then uploaded the XeLL image (All using J-Runner v0.3 Beta (3)).
After playing about alot with the switches, i have it booting, not amazingly fast - but that can be tweaked later.

Switches:
3 -> ON
7 -> ON, due to board type
8 -> ON, due to board type

JTAG - ON (of course)

3-way switch, at "0" position. (in pics its in middle as was trying it)


I thought i had bricked the console, so i flashed back stock nand (nanddump1.bin), unsoldered the 5v to the board - and the console booted absolutely fine.
Reflashed XeLL (jasper.bin that J-Runner makes) And again, when it eventually glitches i get E79, A bottom-right red light on the ring, and an additional error code of 1033.
Done some googling etc and it seems to be coming to a harddrive fault?! the xbox HDD isnt even plugged?! So i thaught, ahh, thats the problem. Plugged the xbox HDD in and then rebooted and still, when it does boot it gets the same.


One of the main error/PANIC is:
POST A0 - VERIFY_SECOTP_6

Heres some of the POST (will reflash the nand with XeLL to show post for that aswell)

Scroll all the way to the bottom of the post if you would like to see the boot in which it did glitch, but of course got E79..
Code: 
===================================================[COLOR=#222222][COLOR=#333333]
[/COLOR][/COLOR]Thursday 05 December 2013 07:08:04 PM


J-Runner v0.3 Beta (3) Started




WARNING! - Your selected working directory already contains files!
You can view these files by using 'Show Working Folder' Button




Checking Files
Finished Checking Files
Initializing nanddump2.bin..
Jasper 16MB
Jtag Selected
Nand Initialization Finished
R-Jtag Selected
Patching Jasper version 2.3 SMC at offset 0x12BA
XeLL file created Successfully jasper.bin
Version: 10
Flash Config: 0x00023010
Writing Nand
jasper.bin
Done!
in 0:18 min:sec


Version: 10
Press Escape to exit
Waiting for POST to change
Post 42 - FETCH_HEADER
Post F2 - Panic - SHA_VERIFY_CB_B
Post C2 - LZX_EXPAND_2
Post F2 - Panic - SHA_VERIFY_CB_B
Post C2 - LZX_EXPAND_2
Post E2
Post F2 - Panic - SHA_VERIFY_CB_B
Post E2
Post F2 - Panic - SHA_VERIFY_CB_B
Post E2
Post F2 - Panic - SHA_VERIFY_CB_B
Post E2
Post F2 - Panic - SHA_VERIFY_CB_B
Post E2
Post F2 - Panic - SHA_VERIFY_CB_B
Post E2
Post F2 - Panic - SHA_VERIFY_CB_B
Post E2
Post F2 - Panic - SHA_VERIFY_CB_B
Post E2
Post F2 - Panic - SHA_VERIFY_CB_B
Post E2
Post F2 - Panic - SHA_VERIFY_CB_B
Post E2
Post FB
Post 10 - Payload/1BL started
Post 18 - FETCH_CONTENTS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 20 - CB entry point reached
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post FE
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 3E
Post 7E
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post E0
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 43 - VERIFY_HEADER
Post C3 - LZX_EXPAND_3
Post E3
Post F3 - Panic - ENTRY_SIZE_INVALID_CB_B
Post FB
Post F3 - Panic - ENTRY_SIZE_INVALID_CB_B
Post FB
Post F3 - Panic - ENTRY_SIZE_INVALID_CB_B
Post 43 - VERIFY_HEADER
Post F3 - Panic - ENTRY_SIZE_INVALID_CB_B
Post 03
Post 01
Post F1 - Panic - VERIFY_HEADER_CB_B
Post 01
Post 40 - Entrypoint of CD reached
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 80
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 7E
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 20 - CB entry point reached
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 0C
Post 3E
Post 7E
Post FE
Post 19 - HMACSHA_COMPUTE
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 28 - FETCH_CONTENTS_3BL_CC
Post 08
Post 20 - CB entry point reached
Post 3E
Post 7E
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post 15 - FETCH_OFFSET
Post 18 - FETCH_CONTENTS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post 12 - FSB_CONFIG_RX_STATE
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 15 - FETCH_OFFSET
Post 18 - FETCH_CONTENTS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post 20 - CB entry point reached
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post 15 - FETCH_OFFSET
Post 18 - FETCH_CONTENTS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post 20 - CB entry point reached
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post 15 - FETCH_OFFSET
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 15 - FETCH_OFFSET
Post 18 - FETCH_CONTENTS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 15 - FETCH_OFFSET
Post 18 - FETCH_CONTENTS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post A0 - Panic - VERIFY_SECOTP_6
Post 80
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 01
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 6C - INIT_SECURITY
Post 6D - INIT_KEY_EX_VAULT
Post 6E - INIT_SETTINGS
Post 70 - INIT_VIDEO_DRIVER
Post 79 - LOAD_XAM
The last line there, LOAD_XAM, is where it E79's and 4th LED red lights, additional error code is 1033, which is HDD failiure, even if theres no HDD plugged in. I found this:
Code: 
[URL]http://xbox-experts.com/errorcode/E79/1033/[/URL]
Which tallys up with the LOAD_XAM from POST.... seems like it cant find XAM.XEX then, whereever it may be :tongue:


Pictures!
WP_20131205_002.jpgWP_20131205_007.jpgWP_20131205_005.jpgWP_20131205_014.jpgWP_20131205_016.jpgWP_20131205_018.jpgWP_20131205_022.jpgWP_20131205_023.jpgWP_20131205_025.jpgWP_20131205_030.jpgWP_20131205_031.jpgWP_20131205_035.jpg

---- The AUD_CLAMP here, yes it is soldered up, but points one and two are bridged and i didnt tick AUD_CLAMP in J-Runner.

Ive also tried HDMI and S-VIDEO.


(If theres anything ive missed off this post, sorry :p)
Thanks in advance,


-Luke
 
L

Lukeshepp

Noob Account
Dec 3, 2013
4
0
---- The AUD_CLAMP here, yes it is soldered up, but points one and two are bridged and i didnt tick AUD_CLAMP in J-Runner.
Click to expand...
^^ Might not have been very clear - I have bridged 1 and 2 intentionally, to do it WITHOUT aud_clamp, wires are just still soldered there from when 1 and 3 was bridged and when i was doing it WITH aud_clamp


EDIT: Here is a some POST data from a boot on the first glitch (still to E79)!,

Code: 
[/COLOR]Version: 10
Press Escape to exit
Waiting for POST to change
Post 42 - FETCH_HEADER
Post 62 - INIT_PROCESS_OBJECTS
Post 42 - FETCH_HEADER
Post 62 - INIT_PROCESS_OBJECTS
Post 42 - FETCH_HEADER
Post 62 - INIT_PROCESS_OBJECTS
Post 42 - FETCH_HEADER
Post 62 - INIT_PROCESS_OBJECTS
Post 42 - FETCH_HEADER
Post 62 - INIT_PROCESS_OBJECTS
Post 42 - FETCH_HEADER
Post 62 - INIT_PROCESS_OBJECTS
Post 42 - FETCH_HEADER
Post 62 - INIT_PROCESS_OBJECTS
Post 42 - FETCH_HEADER
Post 62 - INIT_PROCESS_OBJECTS
Post 42 - FETCH_HEADER
Post 62 - INIT_PROCESS_OBJECTS
Post 42 - FETCH_HEADER
Post 62 - INIT_PROCESS_OBJECTS
Post 42 - FETCH_HEADER
Post 62 - INIT_PROCESS_OBJECTS
Post 42 - FETCH_HEADER
Post 62 - INIT_PROCESS_OBJECTS
Post F3 - Panic - ENTRY_SIZE_INVALID_CB_B
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 42 - FETCH_HEADER
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 6C - INIT_SECURITY
Post 6D - INIT_KEY_EX_VAULT
Post 6E - INIT_SETTINGS
Post 6F - INIT_POWER_MODE
Post 70 - INIT_VIDEO_DRIVER
Post 71 - INIT_AUDIO_DRIVER
Post 77 - INIT_OTHER_DRIVERS
Post 79 - LOAD_XAM


[COLOR=#333333]
 
Last edited:
BL4K3Y

BL4K3Y

VIP Member
Jul 7, 2010
13,721
118
Colne, Lancashire (UK)
Build another R-JTAG XeLL image with AUD_CLAMP checked, write it to the console and test with the 330 and 470 resistance options.

Did you check the resistance of J2D2.1 and J2D2.2 to ground?

You should get readings of about 1.5K on each point.
 
L

Lukeshepp

Noob Account
Dec 3, 2013
4
0
Okay, so im guessing i would have to bridge 1 + 3 again, so i did, built the aud_clamp, flashed it, switched the 3-way to the middle, jumper to 330 and its glitching in 1 to 3 goes, however still to the E79.

New POST:

Code: 
Resetting................
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 43 - VERIFY_HEADER 
Post 63 - INIT_KERNEL_DEBUGGER 
Post E3 
Post 43 - VERIFY_HEADER 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 73 - INIT_SATA_DRIVER 
Post F3 - Panic - ENTRY_SIZE_INVALID_CB_B 
Post E3 
Post F3 - Panic - ENTRY_SIZE_INVALID_CB_B 
Post E3 
Post F3 - Panic - ENTRY_SIZE_INVALID_CB_B 
Post E3 
Post F3 - Panic - ENTRY_SIZE_INVALID_CB_B 
Post E3 
Post F3 - Panic - ENTRY_SIZE_INVALID_CB_B 
Post E3 
Post F3 - Panic - ENTRY_SIZE_INVALID_CB_B 
Post E3 
Post F3 - Panic - ENTRY_SIZE_INVALID_CB_B 
Post E3 
Post 03 
Post E3 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 80 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 17 - VERIFY_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6C - INIT_SECURITY 
Post 6F - INIT_POWER_MODE 
Post 79 - LOAD_XAM 
Most Fails(cumulative): 0xA0
Shutdown
Which points are J2D2, sorry
 
chase

chase

VIP Member
Apr 11, 2004
1,073
28
Toronto, Canada
your soldering looks dull .. like cold joints .. if it was my console, I would redo the soldering and I would use lots of flux

J2D2 is where your jtag qsb is soldered to.. as Bl4K3Y mentioned, check the two points as that qsb/soldering/wiring is often the cause of E79 errors

also, have you tried going through all the dips, resistance, cpu_rst & voltage settings .. the voltage settings seem like they haven't been used (don't thing it would cause or fix E79 issue but you wanna be sure you've gone through all the settings)

maybe you can also try the transistor method of JTAG wiring
 
Last edited:
L

Lukeshepp

Noob Account
Dec 3, 2013
4
0
Off to work now so will try tonight,
On the jtag board the solder joints kept going cold (dull), I had borrowed some flux from work, and its gone back now, but i have my own on its way so ill use it when it gets here, shouldn't be long.

Nope i haven't used the voltage setting, i was just assuming this would just fine tune boot speeds, which i would do after its all working.
Will update tonight
 
D

DayvG

VIP Member
Apr 26, 2007
473
0
Gosport, UK
Looking at your soldering it doesn't look particularly bad, although some do look dry or dull. I would personally get some decent flux and redo most of the points. But before you start again I'd have a good clean up of the board and all the points, it just kinda looks mucky all around where you've been working. I like to keep my work clean. Keil423 has some great guides on YouTube, take a look at how clean his work is. The cleaner the better. Good luck :)


Doing my thing using Tapatalk
 
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