FIXED R-JTAG Jasper wont boot to XELL

lei_55

Junior Member
Jun 2, 2013
18
0
United Kingdom
Console Type: (Jasper)
NAND size: 16
Dashboard version: 2.0.16203
CB version: e.g 6754
Screenshot of NAND details from J-Runner:

Original Nand
jasper_orig_nand.jpg

XELL Reloaded Written

jasper_aud_clamp_xell.jpg

J-Runner log:

===================================================
Thursday, May 30, 2013 5:13:46 PM


J-Runner v0.2 Beta (289) Started




WARNING! - Your selected working directory already contains files!
You can view these files by using 'Show Working Folder' Button




Checking Files
Finished Checking Files
Version: 10
Flash Config: 0x00023010




Initializing nanddump1.bin..
Nand Initialization Finished
Comparing...
Nands are the same
Checking Console..
Version: 10
Flash Config: 0x00023010
Options.ini file was altered successfully
Patching Jasper version 2.3 SMC at offset 0x12BA
XeLL file created Successfully jasper_hack_aud_clamp.bin
Version: 10
Flash Config: 0x00023010
Writing Nand
jasper_hack_aud_clamp.bin
Done!
in 0:18 min:sec

POST output from J-Runner Rater

Voltage default/open
Aud_clamp On / Resistor 470

DIP7,8,5
Version: 10
Power Up
Waiting for POST to change
Post 60 - INIT_KERNEL
Post 60 - INIT_KERNEL
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 20 - CB entry point reached
Post 70 - INIT_VIDEO_DRIVER
Post 78 - INIT_STFS_DRIVER
Post 08
Post 78 - INIT_STFS_DRIVER
Post 08
Post 78 - INIT_STFS_DRIVER
Post 48 - SHA_COMPUTE
Post 78 - INIT_STFS_DRIVER
Post 08
Post 78 - INIT_STFS_DRIVER
Post 48 - SHA_COMPUTE
Post 78 - INIT_STFS_DRIVER
Post 08
Post 48 - SHA_COMPUTE
Post 78 - INIT_STFS_DRIVER
Post 48 - SHA_COMPUTE
Post 78 - INIT_STFS_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 78 - INIT_STFS_DRIVER
Post 08
Post 78 - INIT_STFS_DRIVER
Post 48 - SHA_COMPUTE
Post 78 - INIT_STFS_DRIVER
Post 08
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 20 - CB entry point reached
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 40 - Entrypoint of CD reached
Post 70 - INIT_VIDEO_DRIVER
Post 40 - Entrypoint of CD reached
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 15 - FETCH_OFFSET
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 20 - CB entry point reached
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 40 - Entrypoint of CD reached
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 70 - INIT_VIDEO_DRIVER
Post 40 - Entrypoint of CD reached
Post 70 - INIT_VIDEO_DRIVER
Post 60 - INIT_KERNEL
Post 10 - Payload/1BL started
Post 15 - FETCH_OFFSET
Post 19 - HMACSHA_COMPUTE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 20 - CB entry point reached
Most Fails(cumulative): 0x21
Shutdown
Reached No. of Boots Required

With 1.2v I get RROD 0010 on all DIPS

With 1.8V no RROD
Version: 10
Power Up
Waiting for POST to change
Post 40 - Entrypoint of CD reached
Post 75 - INIT_DUMP_SYSTEM
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 10 - Payload/1BL started
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 01
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 10 - Payload/1BL started
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 01
Shutdown

No RROD but wont boot to XELL..

20130602_181951.jpg

Main Issue: It wont boot to XELL
I dumped my Nand and had no problems and got matching Nand dumps
Created Xell reloaded and wrote it. Reboot and wouldn't boot to XELL. Tried different dips and no go. Tried 1.2v and would just get RROD 0010.. Tried 1.8v no RROD but still will not boot. Tried both bottom and topside CPU_RST. Oiginal nand boots fine. I tried different resistor settings and on different dips but still no Xell. I am not sure if I have the right jasper_aud_clamp.bin file. Original CB is 6754 but after writing Xell it becomes CB 6723, Is this right? I tried doing a falcon and that one worked and the original nand and xell image has the same CB version. Could my problem be the Jrunner file for CB 6754 Jasper.. shout the XELL image be the same CB version as the original nand CB..

Thanks in advance
 

JohnWestBear

VIP Member
Jun 2, 2013
235
0
UK
Did you have any Bad Blocks on your original Nand?

Have you tried moving the bottom QSB to position 0 or moving the jumper to 330 and trying that? or are you just changing Dip settings. Also need pictures of full install not just the Post out board and J Runner.
 

lei_55

Junior Member
Jun 2, 2013
18
0
United Kingdom
1.8v
6,7,8 DIPS on

Version: 10
Power Up
Waiting for POST to change
Post 25 - LOCATE_3BL_CC
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 20 - CB entry point reached
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 20 - CB entry point reached
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 20 - CB entry point reached
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 10 - Payload/1BL started
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 20 - CB entry point reached
Most Fails(cumulative): 0x21
 
Last edited:

lei_55

Junior Member
Jun 2, 2013
18
0
United Kingdom
I'll try to get better pics.. I only have my phone to take pics now as I can't find where I put my camera lenses (another problem)
Yes I tried three different settings on the JTAG qsb and then after that tried different DIPS.
I have no bad blocks on my nand.
I erased the nand before going back to stock and then tried again creating xell and wrote again but same.
 

lei_55

Junior Member
Jun 2, 2013
18
0
United Kingdom
Any reason why you used the alt CPU RST point and didn't put it on the underside?
I originally used the underside CPU_RST but got same results.. Although I only tried underside with default voltage setting which is open.. I might try it again later.. I will try to make the wires as short as possible first and try all dips and voltage setings again on the top side CPU_RST and if that fails then i will go back to bottom side.. I will do that this afternoon and post back.. Thanks..
 

Brad1023

Full Member
Dec 1, 2011
76
0
Florida
Can we get pics of your post out specifically the post 7 point?

My recommendations
1. Go back to the default cpu_rst Point
Note: When trying to figure out timing it's good to anchor this wire, even if you have to remove it later to test the alt point. You always want to test with this wire\ anchored in a permanent fashion so that the pulse being sent is reliable.
2. On J2B1 make sure the wire goes through the hole for E,F,K,and 5V
3. I had issues with my JTAG qsb so I decided to go old fashioned with an original JTAG wiring (that might work for you)
Also Go to Jrunner>Custom Nand/CR Functions erase 16
Flash your original nand back to the Xbox and make sure that your Xbox will Boot to a retail nand with the glitch hardware installed and connected. Run the CR3 Rater and look at the log it generates for a retail image.
After you have your xbox booting the retail nand withing 1 cycle to 0 cycles I would then create your Xell reloaded and then flash it and then try it.
 

Ubergeek

Xecuter Groupie
Feb 24, 2003
6,259
0
California, USA
even the pics you link to show you how to paste the images into forums posts !

example.....

 

Brad1023

Full Member
Dec 1, 2011
76
0
Florida
Can we get pics of your post out specifically the post 7 point?

My recommendations
1. Go back to the default cpu_rst Point
Note: When trying to figure out timing it's good to anchor this wire, even if you have to remove it later to test the alt point. You always want to test with this wire\ anchored in a permanent fashion so that the pulse being sent is reliable.
2. On J2B1 make sure the wire goes through the hole for E,F,K,and 5V
3. I had issues with my JTAG qsb so I decided to go old fashioned with an original JTAG wiring (that might work for you)
Also Go to Jrunner>Custom Nand/CR Functions erase 16
Flash your original nand back to the Xbox and make sure that your Xbox will Boot to a retail nand with the glitch hardware installed and connected. Run the CR3 Rater and look at the log it generates for a retail image.
After you have your xbox booting the retail nand withing 1 cycle to 0 cycles I would then create your Xell reloaded and then flash it and then try it.
 

lei_55

Junior Member
Jun 2, 2013
18
0
United Kingdom
Can we get pics of your post out specifically the post 7 point?

My recommendations
1. Go back to the default cpu_rst Point
Note: When trying to figure out timing it's good to anchor this wire, even if you have to remove it later to test the alt point. You always want to test with this wire\ anchored in a permanent fashion so that the pulse being sent is reliable.
2. On J2B1 make sure the wire goes through the hole for E,F,K,and 5V
3. I had issues with my JTAG qsb so I decided to go old fashioned with an original JTAG wiring (that might work for you)
Also Go to Jrunner>Custom Nand/CR Functions erase 16
Flash your original nand back to the Xbox and make sure that your Xbox will Boot to a retail nand with the glitch hardware installed and connected. Run the CR3 Rater and look at the log it generates for a retail image.
After you have your xbox booting the retail nand withing 1 cycle to 0 cycles I would then create your Xell reloaded and then flash it and then try it.
After playing with all possible dip setting, switches and with different voltage settings combinations while using top side CPU_RST, Still no boot to xell without any errors. Getting RROD 0022 when voltage is at 1.2v no error or RROD with default or 1.8v.

Used bottom side CPU_RST
Erased Nand
Write stock nand
Console boots on stock nand with everything connected except for POST_OUT Ribbon Cable(RROD 0022 when connected).

When using R8C2 as CPU_RST it wont boot to stock nand
Checked continuity from POST qsb to RJTAG ok

R-Jtag Voltage check
5v=4.98v
E=3.29v
F=3.29v
K=3.29v
D=0

I only get the RROD 0022 in stock nand with POST ribbon cable connected but with Xell is written i only get the RROD 0022 when my voltage setting is at 1.2v and no RROD on other voltage settings with everything connected. I wrote Xell back and now no RROD with POST ribbon cable connected but still can't get to boot to Xell..

I am now going to try all possible DIPS while Im at 1.8v

I am starting to run out of ideas on this one.. I've already done four falcons in the last few days and I start working on other xbox when I get frustrated with this Jasper.. Too bad I only have one corona V2 left to work on if a decide to take a rest from this one.


-* *
 
Last edited: