JTAG R-JTAG Zephyr 15574 CB 4569 Post code question

bobgatz · Sep 27, 2013

I had to use JTAG as the prefix on this post since R-JTAG is not available as an option.

I installed the R-JTAG ultimate kit on a phat zephyr dash 15574 with CB of 4569. Can't post pictures because I have no camera at present. Anyhow, I was able to dump 4 copies of the retail nand (no errors or bad bad blocks, and they checked out identical). I created the Xell reloaded, and wrote it to the nand, and attempted to boot. Went through all combinations of options and finally, finally was able to boot once and got the cpu key. The successful boot occurred with the voltage jumper set to 1.2, the resistor option set to 0, the aud clamp option on, and only dip sw 2 set. Attached is a partial log from jrunner.

My question is: why am i getting a bunch of Post 70 - INIT_VIDEO_DRIVER at the beginning of the glitch process? Should these post 70's really be Post F0 - Panic - VERIFY_OFFSET_CB_B? In other words, is the coolrunner sometimes missing bit 7 on the post codes, and is that why I am having trouble with booting?

The console still boots fine with the original nand by simply disconnecting the flat post cable.

BL4K3Y · Sep 28, 2013

The POST output looks fine to me, but there appears to be a "floating" signal somewhere which is why you are getting those random POST codes (don't worry about these).

Complete this template please.

bobgatz · Sep 28, 2013

Here is the info as requested by the template:
Console Type: Zephyr
NAND size: 16
Dashboard version: 2.0.15574.0
CB version: 4569
J-Runner log:

Code:

****** Created Xell reloaded from read of retail nand (no errors or bad blocks)
****** Wrote to nand . . . following is log of only successful boot

****** Zephyr dash 2.0.15574.0
****** CB 4659
****** R-JTAG Ultimate kit
****** Voltage jumper 1.2V
****** Resistor switch 0
****** Aud Clamp option

Waiting for POST to change
Post A0 - Panic - VERIFY_SECOTP_6
Post E0
Post C0
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 15 - FETCH_OFFSET
Post 18 - FETCH_CONTENTS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 15 - FETCH_OFFSET
Post 18 - FETCH_CONTENTS
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post 70 - INIT_VIDEO_DRIVER
Post C0
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 39 - SHA_VERIFY_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 42 - FETCH_HEADER
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 6C - INIT_SECURITY
Post 6D - INIT_KEY_EX_VAULT
Post 6E - INIT_SETTINGS
Post 6F - INIT_POWER_MODE
Post 70 - INIT_VIDEO_DRIVER
Done!


*******Xbox was hung, so shut off console and restarted

Version: 10
Press Escape to exit
Waiting for POST to change
Post A0 - Panic - VERIFY_SECOTP_6
Post E0
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post 80
Post F0 - Panic - VERIFY_OFFSET_CB_B
Post B0 - Panic - VERIFY_CONSOLE_TYPE
Post 12 - FSB_CONFIG_RX_STATE
Post 15 - FETCH_OFFSET
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 42 - FETCH_HEADER
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Done!

******** This was my 1 and only successful boot
******** Managed to get CPU Key!

****** Tried to boot again, no luck


****** Wrote back original nand, and boots fine with post cable unconnected.

updflash.bin log (if applicable):
Description of problem: Only booted once out of hundreds of tries

Was the console working before you started: Yes

Console still working after installation: Yes

An explanation of R2P12 repair: The Jtag QSB got snagged when turning over the motherboard, and R2P12 got broken and lifted the traces connected to it. I had to remove the QSB, repair the traces, and replace the 10K resistor with what I had. Also, on the QSBv3, after the console wouldn't boot, I removed the QSB to check for shorts underneath, and when resoldering it, I felt it would be better to solder the end connection to a safer location.

Martin C · Sep 28, 2013

Your console needs professional attention.

XMonsterModsX · Sep 28, 2013

that consoles soldering looks horrible no wonder u cant get it to boot on rgh side

tomma66 · Sep 28, 2013

As Martin has said you need to get a pro to sort that out the soldering is terrible.

bobgatz · Sep 28, 2013

OK, the soldering is terrible, but the console still works perfectly with the original nand. I still want to know if the post 70's at the beginning of the glitch cycles should really be F0's. As I understand the process, the Coolrunner monitors the post data and uses it to generate a glitch at the correct time. Is that correct?

bobgatz · Sep 30, 2013

It looks like no one wants to answer my questions because of my "terrible" soldering. However, I think that what is important in soldering is that there is no bridging, and that the connections are good. Anyway, I will keep on asking questions, and maybe it will stimulate someone else from posting in a similar situation, and I can learn from their responses.

In an effort to try to get more consistent results, I tried various combinations of setting options and still have best results with 1v2, sw2, 330 ohms and aud clamp. (Have not tried without aud clamp . . . will do that soon.) This is done with "xell reloaded" written to the nand, cause I wanted to find the best settings before creating a full image. This time I tried rater instead of post monitor and here are the log outputs.

My new question is: Does rater think that the boots are successful? If so, it is out to lunch, because the screen stays blank. Or, does the console indeed boot but needs the component video cable output to show on the screen? I have only the hdmi cable, and there is no video output.

Code:

Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Shutdown
Power Up
Waiting for POST to change
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 94 - Panic - VERIFY_OFFSET 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 15 - FETCH_OFFSET 
Post 18 - FETCH_CONTENTS 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6C - INIT_SECURITY 
Post 6F - INIT_POWER_MODE 
Shutdown
Power Up
Waiting for POST to change
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post C0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6C - INIT_SECURITY 
Post 6D - INIT_KEY_EX_VAULT 
Post 6F - INIT_POWER_MODE 
Most Fails(cumulative): 0xA0
Shutdown
Power Up
Waiting for POST to change
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 43 - VERIFY_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6C - INIT_SECURITY 
Most Fails(cumulative): 0xA0
Shutdown
Power Up
Waiting for POST to change
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 69 - INIT_KEY_VAULT 
Post 6C - INIT_SECURITY 
Post 70 - INIT_VIDEO_DRIVER 
Most Fails(cumulative): 0xA0
Shutdown
Reached No. of Boots Required

Martin C · Sep 30, 2013

6C-6F is normally due to the JTAG side of your soldering.

So, once again - get someone to fix it for you.

bobgatz · Sep 30, 2013

OK, I will clean up the Jtag soldering and post new pictures. However, I can't do anything about the R2P12 repair and will leave it as is since it is working OK. Also a correction on my previous post about settings. The tests were done with a resistor setting of 0 ohms, not 330.

Martin C · Sep 30, 2013

Check resistance of J2D2.1 against GND, also J2D2.2 against GND.

bobgatz · Sep 30, 2013

Good results this time. I cleaned up the solder points, and decided to try a Falcon Xell reloaded. With the same option settings as before, I got it to boot to Xell 5 times out of 5. Log and screen shots below. I will now proceed to try to boot to a full image. Should I stick with Falcon or revert to Zephyr?

Incidentally, I had tried it first with switch setting 3, and the sw1, before going to sw2. Both 3 and 1 sometimes went further than Post 21, but usually ended up with 6C. Post code 6C definitely results in no video on the screen.

J2D2.1 and .2 measure 1.554K to gnd.

Code:

Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post A0 - Panic - VERIFY_SECOTP_6 
Post E0 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post D0 - CB_A entry point reached 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post D0 - CB_A entry point reached 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Power Up
Waiting for POST to change
Post A0 - Panic - VERIFY_SECOTP_6 
Post E0 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 94 - Panic - VERIFY_OFFSET 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 40 - Entrypoint of CD reached 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post C0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 70 - INIT_VIDEO_DRIVER 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post C0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 70 - INIT_VIDEO_DRIVER 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Power Up
Waiting for POST to change
Post A0 - Panic - VERIFY_SECOTP_6 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Power Up
Waiting for POST to change
Post 30 - VERIFY_OFFSET_4BL_CD 
Post A0 - Panic - VERIFY_SECOTP_6 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post 12 - FSB_CONFIG_RX_STATE 
Post 18 - FETCH_CONTENTS 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Power Up
Waiting for POST to change
Post A0 - Panic - VERIFY_SECOTP_6 
Post E0 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Reached No. of Boots Required

- - - Updated - - -

Good results this time. I cleaned up the solder points, and decided to try a Falcon Xell reloaded. With the same option settings as before, I got it to boot to Xell 5 times out of 5. Log and screen shots below. I will now proceed to try to boot to a full image. Should I stick with Falcon or revert to Zephyr?

Incidentally, I had tried it first with switch setting 3, and the sw1, before going to sw2. Both 3 and 1 sometimes went further than Post 21, but usually ended up with 6C. Post code 6C definitely results in no video on the screen.

J2D2.1 and .2 measure 1.554K to gnd.

Code:

Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post A0 - Panic - VERIFY_SECOTP_6 
Post E0 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post D0 - CB_A entry point reached 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post D0 - CB_A entry point reached 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Power Up
Waiting for POST to change
Post A0 - Panic - VERIFY_SECOTP_6 
Post E0 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 94 - Panic - VERIFY_OFFSET 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 40 - Entrypoint of CD reached 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post C0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 70 - INIT_VIDEO_DRIVER 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post C0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 30 - VERIFY_OFFSET_4BL_CD 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 70 - INIT_VIDEO_DRIVER 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Power Up
Waiting for POST to change
Post A0 - Panic - VERIFY_SECOTP_6 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Power Up
Waiting for POST to change
Post 30 - VERIFY_OFFSET_4BL_CD 
Post A0 - Panic - VERIFY_SECOTP_6 
Post E0 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post 12 - FSB_CONFIG_RX_STATE 
Post 18 - FETCH_CONTENTS 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Power Up
Waiting for POST to change
Post A0 - Panic - VERIFY_SECOTP_6 
Post E0 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 80 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Shutdown
Reached No. of Boots Required

Martin C · Sep 30, 2013

try a Zephyr_aud_clamp xell. that will tell you whether you'll need a falcon freeboot image.

bobgatz · Oct 1, 2013

I built the Zephyr image with Rjtag and aud clamp selected, wrote it to the nand, but have no cluck in booting it. It fonly goes through the initial post codes and stops at 21. I can upload the updflash.bin log if needed. However, it seems to me that it is way too far from booting. I also tried changing the switch from 1 through 6.

pengekcs · Oct 1, 2013

As in the manual, extract the files from your original nand. Rename kv_en.bin to kv.bin, smc_en.bin to smc.bin and copy these + the smc_config.bin file (3 files) over to jrunner dir/xebuild/data overwriting anything that might be there.

Look up the higher LDV value from your original nand dump (this must be 8 based on your images above)

Now with your cpu key entered (and no nand file loaded) choose falcon as motherboard type, tick rjtag and aud_clamp then use the advanced / create nand file without nanddump.bin (or whatever its name) -- and whoops you got a falcon based rjtag image ready to be written to your xbox.

Anyway thanks for this thread, I got a machine with the same problem always stuck on 6B-6F (with qsb and with plain diodes as well). Points looked clean though.

bobgatz · Oct 1, 2013

I followed the directions from pengekcs, created a falcon image, and wrote it to the nand. I managed to boot it once after several tries, and was presented with a new setup screen. I went through the process and then shut down the console. I then set jrunner to use rater for 5 boots, and the results are attached. Out of the 5 boots reported by rater, only one actually booted. Any suggestions on what to try to get it more reliable? I currently have the board sitting on the desk, but with the dvd and hard disk attached, so that I can try different options more readily. I will try putting it back in the chassis and see if that still works. The settings currently are the same as the last post, namely: 1.2v, aud_clamp, 0 ohms and sw2.

Code:

Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post 15 - FETCH_OFFSET 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 20 - CB entry point reached 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 10 - Payload/1BL started 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 62 - INIT_PROCESS_OBJECTS 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Shutdown
Power Up
Waiting for POST to change
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F8 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post 70 - INIT_VIDEO_DRIVER 
Post F8 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 15 - FETCH_OFFSET 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Shutdown
Power Up
Waiting for POST to change
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F8 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post 70 - INIT_VIDEO_DRIVER 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post 70 - INIT_VIDEO_DRIVER 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 15 - FETCH_OFFSET 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post 20 - CB entry point reached 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post 60 - INIT_KERNEL 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post 60 - INIT_KERNEL 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 18 - FETCH_CONTENTS 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 59 - INIT_SOC_MMIO 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1A - RC4_INITIALIZE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 23 - INIT_SYSRAM 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3B - PCI_INIT 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 49 - SHA_VERIFY 
Post 4B - LZX_EXPAND 
Post 4D - DECODE_FUSES 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Most Fails(cumulative): 0xA0
Shutdown
Power Up
Waiting for POST to change
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 23 - INIT_SYSRAM 
Post 2E - HWINIT 
Post FC 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post C0 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 14 - FSB_CONFIG_TX_CREDITS 
Post 15 - FETCH_OFFSET 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post FC 
Post F8 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post FC 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post 70 - INIT_VIDEO_DRIVER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 31 - FETCH_HEADER_4BL_CD 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 61 - INIT_HAL_PHASE_0 
Post 63 - INIT_KERNEL_DEBUGGER 
Post 64 - INIT_MEMORY_MANAGER 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Most Fails(cumulative): 0xA0
Shutdown
Power Up
Waiting for POST to change
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post B0 - Panic - VERIFY_CONSOLE_TYPE 
Post A0 - Panic - VERIFY_SECOTP_6 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F8 
Post F8 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 18 - FETCH_CONTENTS 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post F8 
Post 15 - FETCH_OFFSET 
Post 18 - FETCH_CONTENTS 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F8 
Post 20 - CB entry point reached 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post 60 - INIT_KERNEL 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post 10 - Payload/1BL started 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post A0 - Panic - VERIFY_SECOTP_6 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post 20 - CB entry point reached 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 15 - FETCH_OFFSET 
Post 16 - FETCH_HEADER 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F0 - Panic - VERIFY_OFFSET_CB_B 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post F8 
Post 10 - Payload/1BL started 
Post 11 - FSB_CONFIG_PHY_CONTROL 
Post 12 - FSB_CONFIG_RX_STATE 
Post 13 - FSB_CONFIG_TX_STATE 
Post 15 - FETCH_OFFSET 
Post 18 - FETCH_CONTENTS 
Post 19 - HMACSHA_COMPUTE 
Post 1B - RC4_DECRYPT 
Post 1C - SHA_COMPUTE 
Post 1D - SIG_VERIFY 
Post 1E - BRANCH 
Post 20 - CB entry point reached 
Post 21 - INIT_SECOTP 
Post 22 - INIT_SECENG 
Post 2F - RELOCATE 
Post 2E - HWINIT 
Post 33 - FETCH_CONTENTS_4BL_CD 
Post 34 - HMACSHA_COMPUTE_4BL_CD 
Post 35 - RC4_INITIALIZE_4BL_CD 
Post 36 - RC4_DECRYPT_4BL_CD 
Post 37 - SHA_COMPUTE_4BL_CD 
Post 3A - BRANCH 
Post 40 - Entrypoint of CD reached 
Post 42 - FETCH_HEADER 
Post 44 - FETCH_CONTENTS 
Post 45 - HMACSHA_COMPUTE 
Post 46 - RC4_INITIALIZE 
Post 47 - RC4_DECRYPT 
Post 48 - SHA_COMPUTE 
Post 4B - LZX_EXPAND 
Post 4E - FETCH_OFFSET_6BL_CF 
Post 4F - VERIFY_OFFSET_6BL_CF 
Post 51 - LOAD_UPDATE_2 
Post 50 - LOAD_UPDATE_1 
Post 52 - BRANCH 
Post 58 - INIT_HYPERVISOR 
Post 5A - INIT_XEX_TRAINING 
Post 60 - INIT_KERNEL 
Post 61 - INIT_HAL_PHASE_0 
Post 64 - INIT_MEMORY_MANAGER 
Post 65 - INIT_STACKS 
Post 66 - INIT_OBJECT_SYSTEM 
Post 67 - INIT_PHASE1_THREAD 
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS 
Post 69 - INIT_KEY_VAULT 
Post 6A - INIT_HAL_PHASE_1 
Post 6B - INIT_SFC_DRIVER 
Post 6C - INIT_SECURITY 
Most Fails(cumulative): 0xA0
Shutdown
Reached No. of Boots Required

bobgatz · Oct 2, 2013

Update on my progress (or lack thereof):

I put the board back in the cage with the dvd and hard drive connected. The nand is loaded with a Falcon R-Jtag with aud_clamp full image created as explained in the previous post. There doesn't seem to be any difference whether the board is open on the desk, or placed in the cage. "Best" results are obtained with only SW2 on. The boot was definitely more consistent with only Xell reloaded than with a full image. With only Xell reloaded, it would boot most times with an occasional fail. With the full image it fails most times, with an occasional success. When it does boot, everything works fine. I was able to install a game, a DLC and Freedash 3. I am not convinced that a Post code of 6C indicates a Jtag solder problem. Below is a log of my last successful boot, and it has post codes of 6C, 6D, 6E and 6F, but it still booted fine. If the experts are sure that those codes are a soldering problem, I will go over those again.

Code:

Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 42 - FETCH_HEADER
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 49 - SHA_VERIFY
Post 4B - LZX_EXPAND
Post 4D - DECODE_FUSES
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS
Post 5F
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 6C - INIT_SECURITY
Post 6D - INIT_KEY_EX_VAULT
Post 6E - INIT_SETTINGS
Post 6F - INIT_POWER_MODE
Post 70 - INIT_VIDEO_DRIVER
Post 71 - INIT_AUDIO_DRIVER
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init
Post 73 - INIT_SATA_DRIVER
Post 75 - INIT_DUMP_SYSTEM
Post 77 - INIT_OTHER_DRIVERS
Post 78 - INIT_STFS_DRIVER
Post 79 - LOAD_XAM
Done!

jsinger47 · Oct 2, 2013

No, what we are saying is that if the console FAILS on those codes, it is a JTAG wiring issue.

RF1911 · Oct 2, 2013

If you turn it on without rater and it boots dash in a resonable time, close it and play with it.

bobgatz · Oct 5, 2013

Here is an update and a new question. I have tried numerous configurations to try to get better results. I tried both zephyr and falcon images with and without aud_clamp, and tried the full gamut of options with dip sw settings, voltage settings and resistor settings. Took a deal of time for all those. Also tried with the cpu_rst point on the bottom of the board. Currently, I get best results with a falcon image, 1.2V jumper, 0 ohms resistor and bottom cpu_rst point. The console boots maybe 1 out of about 50 tries. It can take up to an hour before it boots, but sometimes it boots on the 1st attempt. With the cpu_rst point on topside, (and with supplied flat cable) it booted maybe once out of about a 100 tries, so this is an improvement.

I had asked a post code question in my first post that never got answered, so I did some experimenting. When I get a lot of post 70 codes at the beginning of the glitch cycle, it took longer to finally boot. By loosening the flat cable connecter latch and repositioning the cable in the connector, I get a bunch of F0 codes instead of 70, and it seems to me that successful boots occur more often. So, I removed the flat cable completely, and soldered my own flat cable between the QSB post pads and the Coolrunner post pads. The results stated above are with my own flat cable.

I don't know what else to try to make the console somewhat usable. (From reading over my post before submission, I can try the topside rst poit with my cable.) The console belongs to my nephew, and I hate to have to reflash the original nand and tell him he can't run homebrew. I had reflashed the Hitachi dvd drive for him a year ago, so he can still run backed-up dvds, but he wanted to load some dlc's.

I appreciate the positive responses on my post, and hopefully there will be some more forthcoming.

My new question: If my nephew is willing to live with up to an hour to boot the console, I need to add a led to the front panel to indicate when the Coolrunner is glitching. Most of the boot failures result in a hang, with the center green led lit. If the glitch led is on the front panel, he can toggle the power button, if there is no activity. Does the Coolrunner chip have enough drive capability to drive another led? I would connect a resistor and led from the Coolrunner R1 point to ground via a 2-wire cable. If there is not enough drive capability, I would have to destroy the coolrunner led and replace it with one on the front panel.

Search

Search

JTAG R-JTAG Zephyr 15574 CB 4569 Post code question

bobgatz

Junior Member

Attachments

BL4K3Y

bobgatz

Junior Member

Attachments

Martin C

XMonsterModsX

BANNED

tomma66

bobgatz

Junior Member

bobgatz

Junior Member

Attachments

Martin C

bobgatz

Junior Member

Martin C

bobgatz

Junior Member

Attachments

Martin C

bobgatz

Junior Member

pengekcs

BANNED

bobgatz

Junior Member

Attachments

bobgatz

Junior Member

jsinger47

RF1911

bobgatz

Junior Member