Console Type: Jasper
NAND size: 16
Dashboard version: ?.?.16537
CB version: 6723
Screenshot of NAND details from J-Runner: See below
Was the console working before you started: Yes
J-Runner logs (from rater):
This one stuck at LOAD_XAM, nothing ever displayed on the screen.
Resistor:470, AUD_CLAMP ON, Bottom CPU_RST, Voltage Select: OPEN, DIPS 7,8 & 3
This one ended in RROD.
Resistor:330, AUD_CLAMP ON, Bottom CPU_RST, Voltage Select: OPEN, DIPS 7,8 & 5
updflash.bin log (if applicable): Not yet available
Image of R-JTAG board: See below
Description of problem:
First of all, thanks to all the contributors of all the threads that I have read over the last week. And thanks for any assistance that may come from this post.
I have not been able to get this console to boot consistently and am about to pull my hair out trying to figure out what is going on. NAND read and write went fine, the console has booted Xell about 3 times out of maybe 100 tries over the last 3 days of messing with it. (And I was able to get the CPU key) Most often lots of "Post A0 - Panic - VERIFY_SECOTP_6", but maybe 20 out of the 100 have ended in a hang at "Post 79 - LOAD_XAM". I'm just trying to figure out if I am on the right path to getting this thing to work, or does anybody see something in these POST logs that indicates a wiring issue or something else? Is there a systematic approach to working the DIPs, resistor values, etc. if the standard ones don't work right out of the gate?
Other questions:
1) I am doing all this with the motherboard out of the case, does it all need to be installed & buttoned up for this to work properly?
2) Do I need to unplug the power brick before I change DIP settings and then replug? (This is what I have been doing)
3) Can someone point me to the FAQ/info on how to get the CPU key info via network boot from Xell.
4) I am also having a problem with J Runner, in that when I try to select a dash, it never shows up in the drop down list, but I will try on a different computer before going further into detail on that.
The sordid details, for anyone who wants to know what I have tried so far...
Installed ultimate kit, verified continuity from back of motherboard to top of QSB on the NAND-X & JRP/NANDX/CR QSB's (Both on top-side of MB). Verified continuity through the trace at the end of the JRP/NANDX/CR QSB from the solder point on the QSB to the end of the resistor on the other side of the trace. On bottom of MB, POST QSB install looks good, but I don't know if there is any way to test it with a voltmeter, JTAG QSB continuity check through board for the fat solder points, desoldered the small via point and resoldered, and checked continuity through the resistor at the end of the board. I'm fairly certain soldering and wiring is all good, but will post pictures this evening.
Points 1-3 are bridged on JTAG QSB, and wire run from AUD_CLAMP pad to the correct point on Q2N1. Using bottom MB point for CPU_RST currently, although I have tried the top one as well. Resistor setting is currently 470, but have tried 330, 0 & off.
Voltage select on the R-JTAG board is currently open, but have tried both 1.2 & 1.8 volt settings.
NAND size: 16
Dashboard version: ?.?.16537
CB version: 6723
Screenshot of NAND details from J-Runner: See below
Was the console working before you started: Yes
J-Runner logs (from rater):
This one stuck at LOAD_XAM, nothing ever displayed on the screen.
Resistor:470, AUD_CLAMP ON, Bottom CPU_RST, Voltage Select: OPEN, DIPS 7,8 & 3
Code:
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post F7
Post D7 - RC4_INITIALIZE_CB_B
Post 17 - VERIFY_HEADER
Post 15 - FETCH_OFFSET
Post 14 - FSB_CONFIG_TX_CREDITS
Post 10 - Payload/1BL started
Post 01
Post 81 - Panic - MACHINE_CHECK
Post 01
Post 01
Post 81 - Panic - MACHINE_CHECK
Post 83 - Panic - DATA_SEGMENT
Post 81 - Panic - MACHINE_CHECK
Post 01
Post 01
Post 03
Post 83 - Panic - DATA_SEGMENT
Post 03
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 19 - HMACSHA_COMPUTE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 31 - FETCH_HEADER_4BL_CD
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 42 - FETCH_HEADER
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 6C - INIT_SECURITY
Post 79 - LOAD_XAM
Most Fails(cumulative): 0xA0
Shutdown
Resistor:330, AUD_CLAMP ON, Bottom CPU_RST, Voltage Select: OPEN, DIPS 7,8 & 5
Code:
Phat Selected
Version: 10
Power Up
Waiting for POST to change
Post 80
Post 80
Post 80
Post C0
Post 80
Post 40 - Entrypoint of CD reached
Post C0
Post 40 - Entrypoint of CD reached
Post 40 - Entrypoint of CD reached
Post C0
Post 40 - Entrypoint of CD reached
Post 40 - Entrypoint of CD reached
Post C0
Post E0
Post C0
Post 40 - Entrypoint of CD reached
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 20 - CB entry point reached
Post 30 - VERIFY_OFFSET_4BL_CD
Post 30 - VERIFY_OFFSET_4BL_CD
Post 70 - INIT_VIDEO_DRIVER
Post 30 - VERIFY_OFFSET_4BL_CD
Most Fails(cumulative): 0xA0
Shutdown
Image of R-JTAG board: See below
Description of problem:
First of all, thanks to all the contributors of all the threads that I have read over the last week. And thanks for any assistance that may come from this post.
I have not been able to get this console to boot consistently and am about to pull my hair out trying to figure out what is going on. NAND read and write went fine, the console has booted Xell about 3 times out of maybe 100 tries over the last 3 days of messing with it. (And I was able to get the CPU key) Most often lots of "Post A0 - Panic - VERIFY_SECOTP_6", but maybe 20 out of the 100 have ended in a hang at "Post 79 - LOAD_XAM". I'm just trying to figure out if I am on the right path to getting this thing to work, or does anybody see something in these POST logs that indicates a wiring issue or something else? Is there a systematic approach to working the DIPs, resistor values, etc. if the standard ones don't work right out of the gate?
Other questions:
1) I am doing all this with the motherboard out of the case, does it all need to be installed & buttoned up for this to work properly?
2) Do I need to unplug the power brick before I change DIP settings and then replug? (This is what I have been doing)
3) Can someone point me to the FAQ/info on how to get the CPU key info via network boot from Xell.
4) I am also having a problem with J Runner, in that when I try to select a dash, it never shows up in the drop down list, but I will try on a different computer before going further into detail on that.
The sordid details, for anyone who wants to know what I have tried so far...
Installed ultimate kit, verified continuity from back of motherboard to top of QSB on the NAND-X & JRP/NANDX/CR QSB's (Both on top-side of MB). Verified continuity through the trace at the end of the JRP/NANDX/CR QSB from the solder point on the QSB to the end of the resistor on the other side of the trace. On bottom of MB, POST QSB install looks good, but I don't know if there is any way to test it with a voltmeter, JTAG QSB continuity check through board for the fat solder points, desoldered the small via point and resoldered, and checked continuity through the resistor at the end of the board. I'm fairly certain soldering and wiring is all good, but will post pictures this evening.
Points 1-3 are bridged on JTAG QSB, and wire run from AUD_CLAMP pad to the correct point on Q2N1. Using bottom MB point for CPU_RST currently, although I have tried the top one as well. Resistor setting is currently 470, but have tried 330, 0 & off.
Voltage select on the R-JTAG board is currently open, but have tried both 1.2 & 1.8 volt settings.
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