Console Type: Jasper
NAND size: 256
Dashboard version: 16203
CB version: 6754
Was the console working before you started: Y
Finished an R-Jtag on this Jasper 256MB today. Aud Clamp set ON/MIDDLE/470. DIPS 8-7-6. Standard voltage. CPU-RST to top of mobo alt point running above fan shroud. All standard supplied wires.
Console boots and performs fine but getting the quite disappointing rater score posted above. Have tried with voltage set at 1.2 & 1.8 and various DIPS however with altered voltage J-Runner Rater becomes inaccurate and does not log the amount of cycles correctly. (I have achieved legend and perfecto status when changing the voltage, yet actual time to boot remains the same as with standard voltage.)
Does anyone have any guidance based on my rater output and also if there is a fix for rater when using 1.2v/1.8v.
Many thanks.
NAND size: 256
Dashboard version: 16203
CB version: 6754
Was the console working before you started: Y
Code:
[B][B][B][B][B][B][B][B][B][B][B]Version: 10
Power Up
Waiting for POST to change
Post 05
Post 65 - INIT_STACKS
Post 05
Post 25 - LOCATE_3BL_CC
Post 05
Post 25 - LOCATE_3BL_CC
Post 05
Post 01
Post 07
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 60 - INIT_KERNEL
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 41 - VERIFY_OFFSET
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 61 - INIT_HAL_PHASE_0
Post 63 - INIT_KERNEL_DEBUGGER
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 10 - Payload/1BL started
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 23 - INIT_SYSRAM
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4D - DECODE_FUSES
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS
Post 5F
Post 60 - INIT_KERNEL
Post 6A - INIT_HAL_PHASE_1
Post 6C - INIT_SECURITY
Post 6D - INIT_KEY_EX_VAULT
Post 70 - INIT_VIDEO_DRIVER
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init
Post 73 - INIT_SATA_DRIVER
Post 75 - INIT_DUMP_SYSTEM
Post 77 - INIT_OTHER_DRIVERS
Post 78 - INIT_STFS_DRIVER
Post 79 - LOAD_XAM
Most Fails(cumulative): 0x22
Most Fails(cumulative): 0xA0
Shutdown
Power Up
Waiting for POST to change
Post 05
Post 65 - INIT_STACKS
Post 05
Post 25 - LOCATE_3BL_CC
Post 05
Post 25 - LOCATE_3BL_CC
Post 05
Post 25 - LOCATE_3BL_CC
Post 05
Post 01
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 14 - FSB_CONFIG_TX_CREDITS
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post A0 - Panic - VERIFY_SECOTP_6
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 12 - FSB_CONFIG_RX_STATE
Post 13 - FSB_CONFIG_TX_STATE
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 2E - HWINIT
Post 33 - FETCH_CONTENTS_4BL_CD
Post 34 - HMACSHA_COMPUTE_4BL_CD
Post 35 - RC4_INITIALIZE_4BL_CD
Post 36 - RC4_DECRYPT_4BL_CD
Post 37 - SHA_COMPUTE_4BL_CD
Post 3A - BRANCH
Post 40 - Entrypoint of CD reached
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 46 - RC4_INITIALIZE
Post 47 - RC4_DECRYPT
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4E - FETCH_OFFSET_6BL_CF
Post 4F - VERIFY_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 50 - LOAD_UPDATE_1
Post 52 - BRANCH
Post 58 - INIT_HYPERVISOR
Post 5A - INIT_XEX_TRAINING
Post 60 - INIT_KERNEL
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 64 - INIT_MEMORY_MANAGER
Post 65 - INIT_STACKS
Post 66 - INIT_OBJECT_SYSTEM
Post 67 - INIT_PHASE1_THREAD
Post 68 - Started phase 1 Initialization + INIT_PROCESSORS
Post 69 - INIT_KEY_VAULT
Post 6A - INIT_HAL_PHASE_1
Post 6B - INIT_SFC_DRIVER
Post 10 - Payload/1BL started
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 2F - RELOCATE
Post 23 - INIT_SYSRAM
Post 37 - SHA_COMPUTE_4BL_CD
Post 44 - FETCH_CONTENTS
Post 45 - HMACSHA_COMPUTE
Post 48 - SHA_COMPUTE
Post 4B - LZX_EXPAND
Post 4D - DECODE_FUSES
Post 4E - FETCH_OFFSET_6BL_CF
Post 51 - LOAD_UPDATE_2
Post 52 - BRANCH
Post 59 - INIT_SOC_MMIO
Post 5A - INIT_XEX_TRAINING
Post 5B - INIT_KEYRING
Post 5C - INIT_KEYS
Post 5F
Post 61 - INIT_HAL_PHASE_0
Post 62 - INIT_PROCESS_OBJECTS
Post 64 - INIT_MEMORY_MANAGER
Post 6A - INIT_HAL_PHASE_1
Post 6C - INIT_SECURITY
Post 6D - INIT_KEY_EX_VAULT
Post 6F - INIT_POWER_MODE
Post 72 - INIT_BOOT_ANIMATION + XMADecoder & XAudioRender Init
Post 73 - INIT_SATA_DRIVER
Post 75 - INIT_DUMP_SYSTEM
Post 77 - INIT_OTHER_DRIVERS
Post 78 - INIT_STFS_DRIVER
Post 79 - LOAD_XAM
Most Fails(cumulative): 0xA0
Shutdown
[/B][/B][/B][/B][/B][/B][/B][/B][/B][/B][/B]
Code:
[B][B][B][B][B][B][B][B][B][B][B][B]5, 3, 2, 4, 5,
7, 2, 12, 5, 6,
1, 10, 3, 2, 4,
4, 1, 3, 1, 1,
[/B][/B][/B][/B][/B][/B][/B][/B][/B][/B][/B][/B]
Code:
[B][B][B][B][B][B][B][B][B][B][B][B][B][B][B][B][B][B][B][B][B][B]Overall: 20 / 20
[/B][/B][/B][/B][/B][/B][/B][/B][/B][/B][/B]Average: 4.05
Median: 3.5
Score: 5.20
Cycle 1 - 20.00%
Cycle 2 - 15.00%
Cycle 3 - 15.00%
Cycle 4 - 15.00%
Cycle 5 - 15.00%
Cycle 6 - 5.00%
Cycle 7 - 5.00%
Cycle 10 - 5.00%
Cycle 12 - 5.00%
20% within 1 Cycles
50% within 3 Cycles
80% within 5 Cycles
90% within 7 Cycles
100% within 12 Cycles
Fails most on: 0xA0
[/B][/B][/B][/B][/B][/B][/B][/B][/B][/B][/B]
Code:
02 August 2013 15:31:47
J-Runner v0.2 Beta (289) Started
Checking Files
Finished Checking Files
Version: 10
Flash Config: 0x008A3020
CB Version: 6754
Reading Nand to G:\Hacking\XBox\J-Runner v02 Beta (283) Core Pack\output\nanddump1.bin
Reading Nand
Error: 204 reading block D8E
Done!
in 14:10 min:sec
Reading Nand to G:\Hacking\XBox\J-Runner v02 Beta (283) Core Pack\output\nanddump2.bin
Initializing nanddump1.bin..
Reading Nand
Nand Initialization Finished
Error: 204 reading block D8E
Done!
in 14:13 min:sec
Comparing...Takes a while on big nands
Nands are the same
Version: 10
Flash Config: 0x008A3020
CB Version: 6754
Reading Nand to G:\Hacking\XBox\J-Runner v02 Beta (283) Core Pack\output\nanddump1.bin
Reading Nand
Error: 204 reading block D8E
===================================================
Checking Files
Finished Checking Files
Initializing nanddump1.bin..
Nand Initialization Finished
Patching Jasper version 2.3 SMC at offset 0x12BA
XeLL file created Successfully jasper_hack_bigblock_aud_clamp.bin
Version: 10
Flash Config: 0x008A3020
Writing Nand
jasper_hack_bigblock_aud_clamp.bin
Done!
in 0:17 min:sec
Connection TimeOut
Tip: Load the nand on source to have quicker results.
Connection TimeOut
LockDownValue is 15
CPU Key is
Finished
Initializing nanddump1.bin..
CpuKey is Correct
Added Key to Database
Nand Initialization Finished
Connection TimeOut
Connection TimeOut
Options.ini file was altered successfully
Using edited settings
Load Files Initiliazation Finished
Clean SMC detected
Patching Jasper version 2.3 SMC at offset 0x12BA
16203
Started Creation of the 16203 xebuild image
KV Info saved to file
---------------------------------------------------------------
xeBuild v1.07.561
---------------------------------------------------------------
building jtag image
**************** WARNING *************************
nanddump.bin has NAND memory unit data, make
sure you back up any important data off the
internal MU before flashing a new image!
****************************************************
******* WARNING: could not patch SMC reset limit!
---------------------------------------------------------------
G:\Hacking\XBox\J-Runner v02 Beta (283) Core Pack\253828784205\updflash.bin image built, info:
---------------------------------------------------------------
Console : Jasper (big block)
NAND size : 64MiB + NAND MU area
Build : JTAG
Xell : power on console with console eject button
Serial :
ConsoleId :
MoboSerial:
Mfg Date : 10/12/2008
CPU Key :
1BL Key :
DVD Key :
CF LDV : 15
KV type : type2 (hashed)
---------------------------------------------------------------
xeBuild Finished. Have a nice day.
---------------------------------------------------------------
Saved to G:\Hacking\XBox\J-Runner v02 Beta (283) Core Pack\253828784205
Image is Ready
Version: 10
Flash Config: 0x008A3020
Writing Nand
updflash.bin
Done!
in 14:26 min:sec
==================================================Finished an R-Jtag on this Jasper 256MB today. Aud Clamp set ON/MIDDLE/470. DIPS 8-7-6. Standard voltage. CPU-RST to top of mobo alt point running above fan shroud. All standard supplied wires.
Console boots and performs fine but getting the quite disappointing rater score posted above. Have tried with voltage set at 1.2 & 1.8 and various DIPS however with altered voltage J-Runner Rater becomes inaccurate and does not log the amount of cycles correctly. (I have achieved legend and perfecto status when changing the voltage, yet actual time to boot remains the same as with standard voltage.)
Does anyone have any guidance based on my rater output and also if there is a fix for rater when using 1.2v/1.8v.
Many thanks.
Last edited:
