FALCON Two Falcons, Two CR4 XL's, Zero Glitches Zero Bitches (R-JTAG)

Zeigren

Junior Member
Oct 2, 2010
10
0
Seattle
So I have two different Falcons and two CR4 XL's and neither of them will boot with RJTAG.

So first one:
Console Type: Falcon
Programmer Used: JRP v1.1
NAND Size: 16
Dashboard version:2.0.15574
CB Version: 5774
Was the console working before you started: Y
Do you get a green debug light appear on the CR4 XL chip every 4-5 seconds: Y

2nd One:
Console Type: Falcon
Programmer Used: JRP v1.1
NAND Size: 16
Dashboard version:2.0.16537
CB Version: 5774
Was the console working before you started: Y
Do you get a green debug light appear on the CR4 XL chip every 4-5 seconds: Y


It's 1 AM so I haven't taken any pictures (yet). Both consoles "turn on" as in the CR4 XL Green light comes on as does the Center green light on the 360 ROL but that's it. The CR4 XL green light turns on and off every couple of seconds and it sounds like the fan shuts down for a split second during that time but other then that it just sits there.

Both of them are wire only installs (no QSB) and both are using a "Double Shielded Pro Cable" to the CPU_RST point on the bottom side of the motherboard. Console Two I tired the Aud_Clamp with which doesn't seem to have made a difference. I have tried DIPS 7+3,4,5,34,35,345 as well as adding capacitors and changing the post bit jumpers. None of those things seem to have done anything. I've gone over my solder joints and they all seem good to me at least.

I used J-Runner to read the NAND and create/write Xell-Reloaded with JTAG and RJTAG selected (Aud_Clamp selected on Console Two).

I'm a little at a loss of what to try besides resoldering and trying alt points forever. I've done RGH's and JTAGs but this is my first time with RJTAG and the CR4 XL. Do I need to program the CR4 XL for RJTAG+ or anything like that?

Ideas?
Thanks!
(Also couldn't upload screenshots getting some weird error, will try again later today)
 

Fender1967

Full Member
Oct 11, 2015
41
8
Close up clear pictures of your CR4 install would be very helpful for a start off.
You don't need to program the CR4 glitch chips what so ever as they are already pre-programmed.
For R-Jtag+ install,only Dip 7 on the S1 switchs needs to be ON ( all the other dips on S1 should be OFF ) but good clear up-close pictures of your wiring is a must please.
 

briggs01

VIP Member
Feb 17, 2013
1,324
0
as stated above you need pics of your install no one can guess what the problem is , you need Aud_Clamp with falcon
 

Zeigren

Junior Member
Oct 2, 2010
10
0
Seattle
OooooOOOh Aud_Clamp is required for Falcon, that's good to know.
I'll focus on Falcon Two first then since it has Aud_Clamp already. Here's a Imgur gallery of Falcon Two.

Unfortunately in the process of taking pictures I accidentally bumped and sorta messed up R4B24 (which goes to B on the CR4 XL) so I swapped over to FT2R2 instead. Also both diodes had tape preventing them from making contact with anything I just removed them from the pictures.
 

Zeigren

Junior Member
Oct 2, 2010
10
0
Seattle
Oh the link didn't post at all >.> So here are mad images. Sorry people still on dial-up RIP in Peace. If there is a way to spoiler the pictures let me know. Also still couldn't upload pictures directly to the site from IE, FF, or Chrome from 3 different computers so idk what that is about.
Warning
















 

Zeigren

Junior Member
Oct 2, 2010
10
0
Seattle
So I bought a JR Programmer v2 so I could run the Post Monitor to see what's going on. So far no matter what combination of DIP switches I try my Post looks like this:
Code:
Post 01Post 03
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0E
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Which upon further googling I have no idea what it stopping on that means. Any ideas?
 

Titanfreak736

BANNED
Oct 19, 2014
194
0
oh god that soldering is really sh*tty give it to a pro
 

Oggy

Staff member
Troll Eating Dogs
Mar 1, 2010
3,346
128
can you run the post monitor a little longer ?

While the soldering doesn't look great, it's not the worst and aside from pll bypass, nothing looks like it could cause issues. Don't f**k around with that point too much though, as you'll never repair it (skill level).

Maybe trim it a little but I dont think that's your problem.
 
Last edited:

Zeigren

Junior Member
Oct 2, 2010
10
0
Seattle
Well I've re-soldered everything at this point and shortened some of the wires. I've also taken the capacitor on the CR4 XL out of the equation. Still doesn't make it past Post 25.

Is there any reason to try more then two dips at the same time? So far I've tried with dip 7 on and one by one going through 1-6. Then tried every two dip combination from 1-8. Of course each one with a different post bit setting and letting it try to glitch at least 10 times.

Here's part of the log from my last try with various dip and post bit settings.

Code:
Post 01
Post 03
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 13 - FSB_CONFIG_TX_STATE
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0B
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 10 - Payload/1BL started
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 05
Post 06
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 05
Post 06
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 0E
Post 0F
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0B
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0B
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 05
Post 06
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 09
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0F
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 01
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 03
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 11 - FSB_CONFIG_PHY_CONTROL
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 01
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 0E
Post 0F
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0C
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0F
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0B
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
Post 01
Post 03
Post 04
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 07
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC
 

Mrkazador

Junior Member
Oct 19, 2015
23
0
Did you ever get this fixed? I have the exact same problem with my falcon. Even the post log is the same. Starts at post 15 and ends at 25.
 

Zeigren

Junior Member
Oct 2, 2010
10
0
Seattle
Nope. I even bought the QSB's and redid everything and I still have the same problem I had before. My post still looks like this

Post 01
Post 03
Post 05
Post 06
Post 07
Post 08
Post 09
Post 0A
Post 0B
Post 0C
Post 0D
Post 01
Post 0D
Post 15 - FETCH_OFFSET
Post 16 - FETCH_HEADER
Post 17 - VERIFY_HEADER
Post 18 - FETCH_CONTENTS
Post 19 - HMACSHA_COMPUTE
Post 1A - RC4_INITIALIZE
Post 1B - RC4_DECRYPT
Post 1C - SHA_COMPUTE
Post 1D - SIG_VERIFY
Post 1E - BRANCH
Post 1F
Post 20 - CB entry point reached
Post 21 - INIT_SECOTP
Post 22 - INIT_SECENG
Post 23 - INIT_SYSRAM
Post 24 - VERIFY_OFFSET_3BL_CC
Post 25 - LOCATE_3BL_CC

No matter which switches or post bit I have set or how many hundreds of times I let it try I pretty much get the same results every time. Anyone have any thoughts or ideas? After work tonight I'll take new pictures and post them to show its current state.

EDIT:
Here's a video of what my 360/JRunner/JR Programmer/CR4 XL are doing https://youtu.be/g8OJlP2L8Wc
And here are updated pictures of my current set up
Warning










 
Last edited:

Zeigren

Junior Member
Oct 2, 2010
10
0
Seattle
8 months later and I still can't get this to work.

Altogether now I have three Falcon 360s and three CR4XL's and no matter what combination of with or without aud_clamp, dip switches, post-bit settings, capacitors I try I can't get any of them to work.

But in this time period I've sucessfully R-Jtag'd three trinity's, JTAG'd 6 Xenons, did a mix of RJTAG and RGH on five Jaspers. Yet here I am unable to get any of these Falcons to glitch, well I got one to glitch one time but it never did again.

At this point I'm pretty sure there is a government/big pharma/montesano/chem trails/Nicolas Cage conspiracy that Falcons can be R-Jtag'd using a CR4 XL.

Anything else I can try?
 

Boswell

Noob Account
Jul 29, 2016
5
3
I'm so glad I'm not on my own with this issue, I thought I was going mental! The only way I got it to work was with the mobo out of it's case and no dvd drive attached dips 3-7 postbit 10Ohms. Had to cycle the console for 10mins and then it boot, and would continue to boot within 2 glitches everytime. I sent my xbox to a pro for a rgh 1.2 install using a different chip. The fact that I managed to get it to boot made me think at least I'd done something right, worth trying this just for yr own peace of mind. Good luck!
 
  • Like
Reactions: Zeigren

Zeigren

Junior Member
Oct 2, 2010
10
0
Seattle
Darn. Yeah trying RGH 1.2 sounds like a good idea. I think I have some Coolrunner Rev C's somewhere, but if I can't find those I'll hit you up about getting some chips. All my poor CR4XL's going unused :c

UPDATE:
IT WORKED! Jesus Christ why didn't I try RGH 1.2 before?! I went from no glitches to instaboot on all three using some Coolrunner Rev C's and RGH 1.2.
 
Last edited: